1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Intel Broadwell I2S driver 4 * 5 * Copyright 2019 Google LLC 6 * 7 * Modified from dc i2s/broadwell/broadwell.c 8 */ 9 10 #define LOG_CATEGORY UCLASS_I2S 11 12 #include <common.h> 13 #include <dm.h> 14 #include <i2s.h> 15 #include <asm/io.h> 16 #include "broadwell_i2s.h" 17 18 enum { 19 BDW_SHIM_START_ADDRESS = 0xfb000, 20 BDW_SSP0_START_ADDRESS = 0xfc000, 21 BDW_SSP1_START_ADDRESS = 0xfd000, 22 }; 23 24 struct broadwell_i2s_priv { 25 enum frame_sync_rel_timing_t rel_timing; 26 enum frame_sync_pol_t sfrm_polarity; 27 enum end_transfer_state_t end_transfer_state; 28 enum clock_mode_t sclk_mode; 29 uint sclk_dummy_stop; /* 0-31 */ 30 uint sclk_frame_width; /* 1-38 */ 31 struct i2s_shim_regs *shim; 32 struct broadwell_i2s_regs *regs; 33 }; 34 35 static void init_shim_csr(struct broadwell_i2s_priv *priv) 36 { 37 /* 38 * Select SSP clock 39 * Turn off low power clock 40 * Set PIO mode 41 * Stall DSP core 42 */ 43 clrsetbits_le32(&priv->shim->csr, 44 SHIM_CS_S0IOCS | SHIM_CS_LPCS | SHIM_CS_DCS_MASK, 45 SHIM_CS_S1IOCS | SHIM_CS_SBCS_SSP1_24MHZ | 46 SHIM_CS_SBCS_SSP0_24MHZ | SHIM_CS_SDPM_PIO_SSP1 | 47 SHIM_CS_SDPM_PIO_SSP0 | SHIM_CS_STALL | 48 SHIM_CS_DCS_DSP32_AF32); 49 } 50 51 static void init_shim_clkctl(struct i2s_uc_priv *uc_priv, 52 struct broadwell_i2s_priv *priv) 53 { 54 u32 clkctl = readl(&priv->shim->clkctl); 55 56 /* Set 24Mhz mclk, prevent local clock gating, enable SSP0 clock */ 57 clkctl &= SHIM_CLKCTL_RESERVED; 58 clkctl |= SHIM_CLKCTL_MCLK_24MHZ | SHIM_CLKCTL_DCPLCG; 59 60 /* Enable requested SSP interface */ 61 if (uc_priv->id) 62 clkctl |= SHIM_CLKCTL_SCOE_SSP1 | SHIM_CLKCTL_SFLCGB_SSP1_CGD; 63 else 64 clkctl |= SHIM_CLKCTL_SCOE_SSP0 | SHIM_CLKCTL_SFLCGB_SSP0_CGD; 65 66 writel(clkctl, &priv->shim->clkctl); 67 } 68 69 static void init_sscr0(struct i2s_uc_priv *uc_priv, 70 struct broadwell_i2s_priv *priv) 71 { 72 u32 sscr0; 73 uint scale; 74 75 /* Set data size based on BPS */ 76 if (uc_priv->bitspersample > 16) 77 sscr0 = (uc_priv->bitspersample - 16 - 1) << SSP_SSC0_DSS_SHIFT 78 | SSP_SSC0_EDSS; 79 else 80 sscr0 = (uc_priv->bitspersample - 1) << SSP_SSC0_DSS_SHIFT; 81 82 /* Set network mode, Stereo PSP frame format */ 83 sscr0 |= SSP_SSC0_MODE_NETWORK | 84 SSP_SSC0_FRDC_STEREO | 85 SSP_SSC0_FRF_PSP | 86 SSP_SSC0_TIM | 87 SSP_SSC0_RIM | 88 SSP_SSC0_ECS_PCH | 89 SSP_SSC0_NCS_PCH | 90 SSP_SSC0_ACS_PCH; 91 92 /* Scale 24MHz MCLK */ 93 scale = uc_priv->audio_pll_clk / uc_priv->samplingrate / uc_priv->bfs; 94 sscr0 |= scale << SSP_SSC0_SCR_SHIFT; 95 96 writel(sscr0, &priv->regs->sscr0); 97 } 98 99 static void init_sscr1(struct broadwell_i2s_priv *priv) 100 { 101 u32 sscr1 = readl(&priv->regs->sscr1); 102 103 sscr1 &= SSP_SSC1_RESERVED; 104 105 /* Set as I2S master */ 106 sscr1 |= SSP_SSC1_SCLKDIR_MASTER | SSP_SSC1_SCLKDIR_MASTER; 107 108 /* Enable TXD tristate behavior for PCH */ 109 sscr1 |= SSP_SSC1_TTELP | SSP_SSC1_TTE; 110 111 /* Disable DMA Tx/Rx service request */ 112 sscr1 |= SSP_SSC1_TSRE | SSP_SSC1_RSRE; 113 114 /* Clock on during transfer */ 115 sscr1 |= SSP_SSC1_SCFR; 116 117 /* Set FIFO thresholds */ 118 sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_RFT_SHIFT; 119 sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_TFT_SHIFT; 120 121 /* Disable interrupts */ 122 sscr1 &= ~(SSP_SSC1_EBCEI | SSP_SSC1_TINTE | SSP_SSC1_PINTE); 123 sscr1 &= ~(SSP_SSC1_LBM | SSP_SSC1_RWOT); 124 125 writel(sscr1, &priv->regs->sscr1); 126 } 127 128 static void init_sspsp(struct broadwell_i2s_priv *priv) 129 { 130 u32 sspsp = readl(&priv->regs->sspsp); 131 132 sspsp &= SSP_PSP_RESERVED; 133 sspsp |= priv->sclk_mode << SSP_PSP_SCMODE_SHIFT; 134 sspsp |= (priv->sclk_dummy_stop << SSP_PSP_DMYSTOP_SHIFT) & 135 SSP_PSP_DMYSTOP_MASK; 136 sspsp |= (priv->sclk_dummy_stop >> 2 << SSP_PSP_EDYMSTOP_SHIFT) & 137 SSP_PSP_EDMYSTOP_MASK; 138 sspsp |= priv->sclk_frame_width << SSP_PSP_SFRMWDTH_SHIFT; 139 140 /* Frame Sync Relative Timing */ 141 if (priv->rel_timing == NEXT_FRMS_AFTER_END_OF_T4) 142 sspsp |= SSP_PSP_FSRT; 143 else 144 sspsp &= ~SSP_PSP_FSRT; 145 146 /* Serial Frame Polarity */ 147 if (priv->sfrm_polarity == SSP_FRMS_ACTIVE_HIGH) 148 sspsp |= SSP_PSP_SFRMP; 149 else 150 sspsp &= ~SSP_PSP_SFRMP; 151 152 /* End Data Transfer State */ 153 if (priv->end_transfer_state == SSP_END_TRANSFER_STATE_LOW) 154 sspsp &= ~SSP_PSP_ETDS; 155 else 156 sspsp |= SSP_PSP_ETDS; 157 158 writel(sspsp, &priv->regs->sspsp); 159 } 160 161 static void init_ssp_time_slot(struct broadwell_i2s_priv *priv) 162 { 163 writel(3, &priv->regs->sstsa); 164 writel(3, &priv->regs->ssrsa); 165 } 166 167 static int bdw_i2s_init(struct udevice *dev) 168 { 169 struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev); 170 struct broadwell_i2s_priv *priv = dev_get_priv(dev); 171 172 init_shim_csr(priv); 173 init_shim_clkctl(uc_priv, priv); 174 init_sscr0(uc_priv, priv); 175 init_sscr1(priv); 176 init_sspsp(priv); 177 init_ssp_time_slot(priv); 178 179 return 0; 180 } 181 182 static void bdw_i2s_enable(struct broadwell_i2s_priv *priv) 183 { 184 setbits_le32(&priv->regs->sscr0, SSP_SSC0_SSE); 185 setbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN); 186 } 187 188 static void bdw_i2s_disable(struct broadwell_i2s_priv *priv) 189 { 190 clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN); 191 clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN); 192 } 193 194 static int broadwell_i2s_tx_data(struct udevice *dev, void *data, 195 uint data_size) 196 { 197 struct broadwell_i2s_priv *priv = dev_get_priv(dev); 198 u32 *ptr = data; 199 200 log_debug("data=%p, data_size=%x\n", data, data_size); 201 if (data_size < SSP_FIFO_SIZE) { 202 log_err("Invalid I2S data size\n"); 203 return -ENODATA; 204 } 205 206 /* Enable I2S interface */ 207 bdw_i2s_enable(priv); 208 209 /* Transfer data */ 210 while (data_size > 0) { 211 ulong start = timer_get_us() + 100000; 212 213 /* Write data if transmit FIFO has room */ 214 if (readl(&priv->regs->sssr) & SSP_SSS_TNF) { 215 writel(*ptr++, &priv->regs->ssdr); 216 data_size -= sizeof(*ptr); 217 } else { 218 if ((long)(timer_get_us() - start) > 0) { 219 /* Disable I2S interface */ 220 bdw_i2s_disable(priv); 221 log_debug("I2S Transfer Timeout\n"); 222 return -ETIMEDOUT; 223 } 224 } 225 } 226 227 /* Disable I2S interface */ 228 bdw_i2s_disable(priv); 229 log_debug("done\n"); 230 231 return 0; 232 } 233 234 static int broadwell_i2s_probe(struct udevice *dev) 235 { 236 struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev); 237 struct broadwell_i2s_priv *priv = dev_get_priv(dev); 238 struct udevice *adsp = dev_get_parent(dev); 239 u32 bar0, offset; 240 int ret; 241 242 bar0 = dm_pci_read_bar32(adsp, 0); 243 if (!bar0) { 244 log_debug("Cannot read adsp bar0\n"); 245 return -EINVAL; 246 } 247 offset = dev_read_addr_index(dev, 0); 248 if (offset == FDT_ADDR_T_NONE) { 249 log_debug("Cannot read address index 0\n"); 250 return -EINVAL; 251 } 252 uc_priv->base_address = bar0 + offset; 253 254 /* 255 * Hard-code these values. If other settings are required we can add 256 * this to the device tree. 257 */ 258 uc_priv->rfs = 64; 259 uc_priv->bfs = 32; 260 uc_priv->audio_pll_clk = 24 * 1000 * 1000; 261 uc_priv->samplingrate = 48000; 262 uc_priv->bitspersample = 16; 263 uc_priv->channels = 2; 264 uc_priv->id = 0; 265 266 priv->shim = (struct i2s_shim_regs *)uc_priv->base_address; 267 priv->sfrm_polarity = SSP_FRMS_ACTIVE_LOW; 268 priv->end_transfer_state = SSP_END_TRANSFER_STATE_LOW; 269 priv->sclk_mode = SCLK_MODE_DDF_DSR_ISL; 270 priv->rel_timing = NEXT_FRMS_WITH_LSB_PREVIOUS_FRM; 271 priv->sclk_dummy_stop = 0; 272 priv->sclk_frame_width = 31; 273 274 offset = dev_read_addr_index(dev, 1 + uc_priv->id); 275 if (offset == FDT_ADDR_T_NONE) { 276 log_debug("Cannot read address index %d\n", 1 + uc_priv->id); 277 return -EINVAL; 278 } 279 log_debug("bar0=%x, uc_priv->base_address=%x, offset=%x\n", bar0, 280 uc_priv->base_address, offset); 281 priv->regs = (struct broadwell_i2s_regs *)(bar0 + offset); 282 283 ret = bdw_i2s_init(dev); 284 if (ret) 285 return ret; 286 287 return 0; 288 } 289 290 static const struct i2s_ops broadwell_i2s_ops = { 291 .tx_data = broadwell_i2s_tx_data, 292 }; 293 294 static const struct udevice_id broadwell_i2s_ids[] = { 295 { .compatible = "intel,broadwell-i2s" }, 296 { } 297 }; 298 299 U_BOOT_DRIVER(broadwell_i2s) = { 300 .name = "broadwell_i2s", 301 .id = UCLASS_I2S, 302 .of_match = broadwell_i2s_ids, 303 .probe = broadwell_i2s_probe, 304 .ops = &broadwell_i2s_ops, 305 .priv_auto_alloc_size = sizeof(struct broadwell_i2s_priv), 306 }; 307