1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * TI serdes driver for keystone2.
4  *
5  * (C) Copyright 2014
6  *     Texas Instruments Incorporated, <www.ti.com>
7  */
8 
9 #include <errno.h>
10 #include <common.h>
11 #include <asm/ti-common/keystone_serdes.h>
12 
13 #define SERDES_CMU_REGS(x)		(0x0000 + (0x0c00 * (x)))
14 #define SERDES_LANE_REGS(x)		(0x0200 + (0x200 * (x)))
15 #define SERDES_COMLANE_REGS		0x0a00
16 #define SERDES_WIZ_REGS			0x1fc0
17 
18 #define SERDES_CMU_REG_000(x)		(SERDES_CMU_REGS(x) + 0x000)
19 #define SERDES_CMU_REG_010(x)		(SERDES_CMU_REGS(x) + 0x010)
20 #define SERDES_COMLANE_REG_000		(SERDES_COMLANE_REGS + 0x000)
21 #define SERDES_LANE_REG_000(x)		(SERDES_LANE_REGS(x) + 0x000)
22 #define SERDES_LANE_REG_028(x)		(SERDES_LANE_REGS(x) + 0x028)
23 #define SERDES_LANE_CTL_STATUS_REG(x)	(SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
24 #define SERDES_PLL_CTL_REG		(SERDES_WIZ_REGS + 0x0034)
25 
26 #define SERDES_RESET			BIT(28)
27 #define SERDES_LANE_RESET		BIT(29)
28 #define SERDES_LANE_LOOPBACK		BIT(30)
29 #define SERDES_LANE_EN_VAL(x, y, z)	(x[y] | (z << 26) | (z << 10))
30 
31 #define SERDES_CMU_CFG_NUM		5
32 #define SERDES_COMLANE_CFG_NUM		10
33 #define SERDES_LANE_CFG_NUM		10
34 
35 struct serdes_cfg {
36 	u32 ofs;
37 	u32 val;
38 	u32 mask;
39 };
40 
41 struct cfg_entry {
42 	enum ks2_serdes_clock clk;
43 	enum ks2_serdes_rate rate;
44 	struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
45 	struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
46 	struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
47 };
48 
49 /* SERDES PHY lane enable configuration value, indexed by PHY interface */
50 static u32 serdes_cfg_lane_enable[] = {
51 	0xf000f0c0,     /* SGMII */
52 	0xf0e9f038,     /* PCSR */
53 };
54 
55 /* SERDES PHY PLL enable configuration value, indexed by PHY interface  */
56 static u32 serdes_cfg_pll_enable[] = {
57 	0xe0000000,     /* SGMII */
58 	0xee000000,     /* PCSR */
59 };
60 
61 /**
62  * Array to hold all possible serdes configurations.
63  * Combination for 5 clock settings and 6 baud rates.
64  */
65 static struct cfg_entry cfgs[] = {
66 	{
67 		.clk = SERDES_CLOCK_156P25M,
68 		.rate = SERDES_RATE_5G,
69 		.cmu = {
70 			{0x0000, 0x00800000, 0xffff0000},
71 			{0x0014, 0x00008282, 0x0000ffff},
72 			{0x0060, 0x00142438, 0x00ffffff},
73 			{0x0064, 0x00c3c700, 0x00ffff00},
74 			{0x0078, 0x0000c000, 0x0000ff00}
75 		},
76 		.comlane = {
77 			{0x0a00, 0x00000800, 0x0000ff00},
78 			{0x0a08, 0x38a20000, 0xffff0000},
79 			{0x0a30, 0x008a8a00, 0x00ffff00},
80 			{0x0a84, 0x00000600, 0x0000ff00},
81 			{0x0a94, 0x10000000, 0xff000000},
82 			{0x0aa0, 0x81000000, 0xff000000},
83 			{0x0abc, 0xff000000, 0xff000000},
84 			{0x0ac0, 0x0000008b, 0x000000ff},
85 			{0x0b08, 0x583f0000, 0xffff0000},
86 			{0x0b0c, 0x0000004e, 0x000000ff}
87 		},
88 		.lane = {
89 			{0x0004, 0x38000080, 0xff0000ff},
90 			{0x0008, 0x00000000, 0x000000ff},
91 			{0x000c, 0x02000000, 0xff000000},
92 			{0x0010, 0x1b000000, 0xff000000},
93 			{0x0014, 0x00006fb8, 0x0000ffff},
94 			{0x0018, 0x758000e4, 0xffff00ff},
95 			{0x00ac, 0x00004400, 0x0000ff00},
96 			{0x002c, 0x00100800, 0x00ffff00},
97 			{0x0080, 0x00820082, 0x00ff00ff},
98 			{0x0084, 0x1d0f0385, 0xffffffff}
99 		},
100 	},
101 };
102 
103 static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
104 {
105 	writel(((readl(addr) & (~mask)) | (value & mask)), addr);
106 }
107 
108 static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
109 {
110 	u32 i;
111 
112 	for (i = 0; i < size; i++)
113 		ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
114 }
115 
116 static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
117 				   u32 size, u32 lane)
118 {
119 	u32 i;
120 
121 	for (i = 0; i < size; i++)
122 		ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
123 			       cfg_lane[i].val, cfg_lane[i].mask);
124 }
125 
126 static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes)
127 {
128 	u32 i;
129 
130 	ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
131 	ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
132 
133 	for (i = 0; i < num_lanes; i++)
134 		ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
135 
136 	return 0;
137 }
138 
139 static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
140 {
141 	/* Bring SerDes out of Reset */
142 	ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
143 	if (serdes->intf == SERDES_PHY_PCSR)
144 		ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
145 
146 	/* Enable CMU and COMLANE */
147 	ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
148 	if (serdes->intf == SERDES_PHY_PCSR)
149 		ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
150 
151 	ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
152 }
153 
154 static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
155 {
156 	writel(serdes_cfg_pll_enable[serdes->intf],
157 	       base + SERDES_PLL_CTL_REG);
158 }
159 
160 static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
161 {
162 	if (reset)
163 		ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
164 			       0x1, SERDES_LANE_RESET);
165 	else
166 		ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
167 			       0x0, SERDES_LANE_RESET);
168 }
169 
170 static void ks2_serdes_lane_enable(u32 base,
171 				   struct ks2_serdes *serdes, u32 lane)
172 {
173 	/* Bring lane out of reset */
174 	ks2_serdes_lane_reset(base, 0, lane);
175 
176 	writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
177 				  serdes->rate_mode),
178 	       base + SERDES_LANE_CTL_STATUS_REG(lane));
179 
180 	/* Set NES bit if Loopback Enabled */
181 	if (serdes->loopback)
182 		ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
183 			       0x1, SERDES_LANE_LOOPBACK);
184 }
185 
186 int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
187 {
188 	int i;
189 	int ret = 0;
190 
191 	for (i = 0; i < ARRAY_SIZE(cfgs); i++)
192 		if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate)
193 			break;
194 
195 	if (i >= ARRAY_SIZE(cfgs)) {
196 		puts("Cannot find keystone SerDes configuration");
197 		return -EINVAL;
198 	}
199 
200 	ks2_serdes_init_cfg(base, &cfgs[i], num_lanes);
201 
202 	ks2_serdes_cmu_comlane_enable(base, serdes);
203 	for (i = 0; i < num_lanes; i++)
204 		ks2_serdes_lane_enable(base, serdes, i);
205 
206 	ks2_serdes_pll_enable(base, serdes);
207 
208 	return ret;
209 }
210