1 /* 2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <watchdog.h> 12 #include <asm/io.h> 13 #include <linux/compiler.h> 14 #include <serial.h> 15 #include <asm/arch/clk.h> 16 #include <asm/arch/hardware.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 21 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 22 23 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 24 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 25 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 26 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 27 28 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 29 30 struct uart_zynq { 31 u32 control; /* 0x0 - Control Register [8:0] */ 32 u32 mode; /* 0x4 - Mode Register [10:0] */ 33 u32 reserved1[4]; 34 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 35 u32 reserved2[4]; 36 u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 37 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 38 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 39 }; 40 41 static struct uart_zynq *uart_zynq_ports[2] = { 42 [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, 43 [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, 44 }; 45 46 /* Set up the baud rate in gd struct */ 47 static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, 48 unsigned long clock, unsigned long baud) 49 { 50 /* Calculation results. */ 51 unsigned int calc_bauderror, bdiv, bgen; 52 unsigned long calc_baud = 0; 53 54 /* Covering case where input clock is so slow */ 55 if (clock < 1000000 && baud > 4800) 56 baud = 4800; 57 58 /* master clock 59 * Baud rate = ------------------ 60 * bgen * (bdiv + 1) 61 * 62 * Find acceptable values for baud generation. 63 */ 64 for (bdiv = 4; bdiv < 255; bdiv++) { 65 bgen = clock / (baud * (bdiv + 1)); 66 if (bgen < 2 || bgen > 65535) 67 continue; 68 69 calc_baud = clock / (bgen * (bdiv + 1)); 70 71 /* 72 * Use first calculated baudrate with 73 * an acceptable (<3%) error 74 */ 75 if (baud > calc_baud) 76 calc_bauderror = baud - calc_baud; 77 else 78 calc_bauderror = calc_baud - baud; 79 if (((calc_bauderror * 100) / baud) < 3) 80 break; 81 } 82 83 writel(bdiv, ®s->baud_rate_divider); 84 writel(bgen, ®s->baud_rate_gen); 85 } 86 87 /* Set up the baud rate in gd struct */ 88 static void uart_zynq_serial_setbrg(const int port) 89 { 90 unsigned long clock = get_uart_clk(port); 91 struct uart_zynq *regs = uart_zynq_ports[port]; 92 93 return _uart_zynq_serial_setbrg(regs, clock, gd->baudrate); 94 } 95 96 /* Initialize the UART, with...some settings. */ 97 static void _uart_zynq_serial_init(struct uart_zynq *regs) 98 { 99 /* RX/TX enabled & reset */ 100 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 101 ZYNQ_UART_CR_RXRST, ®s->control); 102 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 103 } 104 105 /* Initialize the UART, with...some settings. */ 106 static int uart_zynq_serial_init(const int port) 107 { 108 struct uart_zynq *regs = uart_zynq_ports[port]; 109 110 if (!regs) 111 return -1; 112 113 _uart_zynq_serial_init(regs); 114 uart_zynq_serial_setbrg(port); 115 116 return 0; 117 } 118 119 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) 120 { 121 if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) 122 return -EAGAIN; 123 124 writel(c, ®s->tx_rx_fifo); 125 126 return 0; 127 } 128 129 static void uart_zynq_serial_putc(const char c, const int port) 130 { 131 struct uart_zynq *regs = uart_zynq_ports[port]; 132 133 while (_uart_zynq_serial_putc(regs, c) == -EAGAIN) 134 WATCHDOG_RESET(); 135 136 if (c == '\n') { 137 while (_uart_zynq_serial_putc(regs, '\r') == -EAGAIN) 138 WATCHDOG_RESET(); 139 } 140 } 141 142 static void uart_zynq_serial_puts(const char *s, const int port) 143 { 144 while (*s) 145 uart_zynq_serial_putc(*s++, port); 146 } 147 148 static int uart_zynq_serial_tstc(const int port) 149 { 150 struct uart_zynq *regs = uart_zynq_ports[port]; 151 152 return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; 153 } 154 155 static int uart_zynq_serial_getc(const int port) 156 { 157 struct uart_zynq *regs = uart_zynq_ports[port]; 158 159 while (!uart_zynq_serial_tstc(port)) 160 WATCHDOG_RESET(); 161 return readl(®s->tx_rx_fifo); 162 } 163 164 /* Multi serial device functions */ 165 #define DECLARE_PSSERIAL_FUNCTIONS(port) \ 166 static int uart_zynq##port##_init(void) \ 167 { return uart_zynq_serial_init(port); } \ 168 static void uart_zynq##port##_setbrg(void) \ 169 { return uart_zynq_serial_setbrg(port); } \ 170 static int uart_zynq##port##_getc(void) \ 171 { return uart_zynq_serial_getc(port); } \ 172 static int uart_zynq##port##_tstc(void) \ 173 { return uart_zynq_serial_tstc(port); } \ 174 static void uart_zynq##port##_putc(const char c) \ 175 { uart_zynq_serial_putc(c, port); } \ 176 static void uart_zynq##port##_puts(const char *s) \ 177 { uart_zynq_serial_puts(s, port); } 178 179 /* Serial device descriptor */ 180 #define INIT_PSSERIAL_STRUCTURE(port, __name) { \ 181 .name = __name, \ 182 .start = uart_zynq##port##_init, \ 183 .stop = NULL, \ 184 .setbrg = uart_zynq##port##_setbrg, \ 185 .getc = uart_zynq##port##_getc, \ 186 .tstc = uart_zynq##port##_tstc, \ 187 .putc = uart_zynq##port##_putc, \ 188 .puts = uart_zynq##port##_puts, \ 189 } 190 191 DECLARE_PSSERIAL_FUNCTIONS(0); 192 static struct serial_device uart_zynq_serial0_device = 193 INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); 194 DECLARE_PSSERIAL_FUNCTIONS(1); 195 static struct serial_device uart_zynq_serial1_device = 196 INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); 197 198 #if CONFIG_IS_ENABLED(OF_CONTROL) 199 __weak struct serial_device *default_serial_console(void) 200 { 201 const void *blob = gd->fdt_blob; 202 int node; 203 unsigned int base_addr; 204 205 node = fdt_path_offset(blob, "serial0"); 206 if (node < 0) 207 return NULL; 208 209 base_addr = fdtdec_get_addr(blob, node, "reg"); 210 if (base_addr == FDT_ADDR_T_NONE) 211 return NULL; 212 213 if (base_addr == ZYNQ_SERIAL_BASEADDR0) 214 return &uart_zynq_serial0_device; 215 216 if (base_addr == ZYNQ_SERIAL_BASEADDR1) 217 return &uart_zynq_serial1_device; 218 219 return NULL; 220 } 221 #else 222 __weak struct serial_device *default_serial_console(void) 223 { 224 #if defined(CONFIG_ZYNQ_SERIAL_UART0) 225 if (uart_zynq_ports[0]) 226 return &uart_zynq_serial0_device; 227 #endif 228 #if defined(CONFIG_ZYNQ_SERIAL_UART1) 229 if (uart_zynq_ports[1]) 230 return &uart_zynq_serial1_device; 231 #endif 232 return NULL; 233 } 234 #endif 235 236 void zynq_serial_initialize(void) 237 { 238 serial_register(&uart_zynq_serial0_device); 239 serial_register(&uart_zynq_serial1_device); 240 } 241 242 #ifdef CONFIG_DEBUG_UART_ZYNQ 243 244 #include <debug_uart.h> 245 246 void _debug_uart_init(void) 247 { 248 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 249 250 _uart_zynq_serial_init(regs); 251 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, 252 CONFIG_BAUDRATE); 253 } 254 255 static inline void _debug_uart_putc(int ch) 256 { 257 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 258 259 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) 260 WATCHDOG_RESET(); 261 } 262 263 DEBUG_UART_FUNCS 264 265 #endif 266