1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 5 */ 6 7 #include <clk.h> 8 #include <common.h> 9 #include <debug_uart.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <fdtdec.h> 13 #include <watchdog.h> 14 #include <asm/io.h> 15 #include <linux/compiler.h> 16 #include <serial.h> 17 18 #define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ 19 #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ 20 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 21 22 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 23 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 24 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 25 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 26 27 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 28 29 struct uart_zynq { 30 u32 control; /* 0x0 - Control Register [8:0] */ 31 u32 mode; /* 0x4 - Mode Register [10:0] */ 32 u32 reserved1[4]; 33 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 34 u32 reserved2[4]; 35 u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 36 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 37 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 38 }; 39 40 struct zynq_uart_priv { 41 struct uart_zynq *regs; 42 }; 43 44 /* Set up the baud rate in gd struct */ 45 static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, 46 unsigned long clock, unsigned long baud) 47 { 48 /* Calculation results. */ 49 unsigned int calc_bauderror, bdiv, bgen; 50 unsigned long calc_baud = 0; 51 52 /* Covering case where input clock is so slow */ 53 if (clock < 1000000 && baud > 4800) 54 baud = 4800; 55 56 /* master clock 57 * Baud rate = ------------------ 58 * bgen * (bdiv + 1) 59 * 60 * Find acceptable values for baud generation. 61 */ 62 for (bdiv = 4; bdiv < 255; bdiv++) { 63 bgen = clock / (baud * (bdiv + 1)); 64 if (bgen < 2 || bgen > 65535) 65 continue; 66 67 calc_baud = clock / (bgen * (bdiv + 1)); 68 69 /* 70 * Use first calculated baudrate with 71 * an acceptable (<3%) error 72 */ 73 if (baud > calc_baud) 74 calc_bauderror = baud - calc_baud; 75 else 76 calc_bauderror = calc_baud - baud; 77 if (((calc_bauderror * 100) / baud) < 3) 78 break; 79 } 80 81 writel(bdiv, ®s->baud_rate_divider); 82 writel(bgen, ®s->baud_rate_gen); 83 } 84 85 /* Initialize the UART, with...some settings. */ 86 static void _uart_zynq_serial_init(struct uart_zynq *regs) 87 { 88 /* RX/TX enabled & reset */ 89 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 90 ZYNQ_UART_CR_RXRST, ®s->control); 91 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 92 } 93 94 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) 95 { 96 if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) 97 return -EAGAIN; 98 99 writel(c, ®s->tx_rx_fifo); 100 101 return 0; 102 } 103 104 int zynq_serial_setbrg(struct udevice *dev, int baudrate) 105 { 106 struct zynq_uart_priv *priv = dev_get_priv(dev); 107 unsigned long clock; 108 109 int ret; 110 struct clk clk; 111 112 ret = clk_get_by_index(dev, 0, &clk); 113 if (ret < 0) { 114 dev_err(dev, "failed to get clock\n"); 115 return ret; 116 } 117 118 clock = clk_get_rate(&clk); 119 if (IS_ERR_VALUE(clock)) { 120 dev_err(dev, "failed to get rate\n"); 121 return clock; 122 } 123 debug("%s: CLK %ld\n", __func__, clock); 124 125 ret = clk_enable(&clk); 126 if (ret && ret != -ENOSYS) { 127 dev_err(dev, "failed to enable clock\n"); 128 return ret; 129 } 130 131 _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); 132 133 return 0; 134 } 135 136 static int zynq_serial_probe(struct udevice *dev) 137 { 138 struct zynq_uart_priv *priv = dev_get_priv(dev); 139 140 _uart_zynq_serial_init(priv->regs); 141 142 return 0; 143 } 144 145 static int zynq_serial_getc(struct udevice *dev) 146 { 147 struct zynq_uart_priv *priv = dev_get_priv(dev); 148 struct uart_zynq *regs = priv->regs; 149 150 if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) 151 return -EAGAIN; 152 153 return readl(®s->tx_rx_fifo); 154 } 155 156 static int zynq_serial_putc(struct udevice *dev, const char ch) 157 { 158 struct zynq_uart_priv *priv = dev_get_priv(dev); 159 160 return _uart_zynq_serial_putc(priv->regs, ch); 161 } 162 163 static int zynq_serial_pending(struct udevice *dev, bool input) 164 { 165 struct zynq_uart_priv *priv = dev_get_priv(dev); 166 struct uart_zynq *regs = priv->regs; 167 168 if (input) 169 return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); 170 else 171 return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); 172 } 173 174 static int zynq_serial_ofdata_to_platdata(struct udevice *dev) 175 { 176 struct zynq_uart_priv *priv = dev_get_priv(dev); 177 178 priv->regs = (struct uart_zynq *)devfdt_get_addr(dev); 179 180 return 0; 181 } 182 183 static const struct dm_serial_ops zynq_serial_ops = { 184 .putc = zynq_serial_putc, 185 .pending = zynq_serial_pending, 186 .getc = zynq_serial_getc, 187 .setbrg = zynq_serial_setbrg, 188 }; 189 190 static const struct udevice_id zynq_serial_ids[] = { 191 { .compatible = "xlnx,xuartps" }, 192 { .compatible = "cdns,uart-r1p8" }, 193 { .compatible = "cdns,uart-r1p12" }, 194 { } 195 }; 196 197 U_BOOT_DRIVER(serial_zynq) = { 198 .name = "serial_zynq", 199 .id = UCLASS_SERIAL, 200 .of_match = zynq_serial_ids, 201 .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, 202 .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), 203 .probe = zynq_serial_probe, 204 .ops = &zynq_serial_ops, 205 .flags = DM_FLAG_PRE_RELOC, 206 }; 207 208 #ifdef CONFIG_DEBUG_UART_ZYNQ 209 static inline void _debug_uart_init(void) 210 { 211 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 212 213 _uart_zynq_serial_init(regs); 214 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, 215 CONFIG_BAUDRATE); 216 } 217 218 static inline void _debug_uart_putc(int ch) 219 { 220 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 221 222 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) 223 WATCHDOG_RESET(); 224 } 225 226 DEBUG_UART_FUNCS 227 228 #endif 229