1 /* 2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <clk.h> 9 #include <common.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <fdtdec.h> 14 #include <watchdog.h> 15 #include <asm/io.h> 16 #include <linux/compiler.h> 17 #include <serial.h> 18 #include <asm/arch/hardware.h> 19 20 #define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ 21 #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ 22 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 23 24 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 25 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 26 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 27 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 28 29 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 30 31 struct uart_zynq { 32 u32 control; /* 0x0 - Control Register [8:0] */ 33 u32 mode; /* 0x4 - Mode Register [10:0] */ 34 u32 reserved1[4]; 35 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 36 u32 reserved2[4]; 37 u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 38 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 39 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 40 }; 41 42 struct zynq_uart_priv { 43 struct uart_zynq *regs; 44 }; 45 46 /* Set up the baud rate in gd struct */ 47 static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, 48 unsigned long clock, unsigned long baud) 49 { 50 /* Calculation results. */ 51 unsigned int calc_bauderror, bdiv, bgen; 52 unsigned long calc_baud = 0; 53 54 /* Covering case where input clock is so slow */ 55 if (clock < 1000000 && baud > 4800) 56 baud = 4800; 57 58 /* master clock 59 * Baud rate = ------------------ 60 * bgen * (bdiv + 1) 61 * 62 * Find acceptable values for baud generation. 63 */ 64 for (bdiv = 4; bdiv < 255; bdiv++) { 65 bgen = clock / (baud * (bdiv + 1)); 66 if (bgen < 2 || bgen > 65535) 67 continue; 68 69 calc_baud = clock / (bgen * (bdiv + 1)); 70 71 /* 72 * Use first calculated baudrate with 73 * an acceptable (<3%) error 74 */ 75 if (baud > calc_baud) 76 calc_bauderror = baud - calc_baud; 77 else 78 calc_bauderror = calc_baud - baud; 79 if (((calc_bauderror * 100) / baud) < 3) 80 break; 81 } 82 83 writel(bdiv, ®s->baud_rate_divider); 84 writel(bgen, ®s->baud_rate_gen); 85 } 86 87 /* Initialize the UART, with...some settings. */ 88 static void _uart_zynq_serial_init(struct uart_zynq *regs) 89 { 90 /* RX/TX enabled & reset */ 91 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 92 ZYNQ_UART_CR_RXRST, ®s->control); 93 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 94 } 95 96 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) 97 { 98 if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) 99 return -EAGAIN; 100 101 writel(c, ®s->tx_rx_fifo); 102 103 return 0; 104 } 105 106 int zynq_serial_setbrg(struct udevice *dev, int baudrate) 107 { 108 struct zynq_uart_priv *priv = dev_get_priv(dev); 109 unsigned long clock; 110 111 int ret; 112 struct clk clk; 113 114 ret = clk_get_by_index(dev, 0, &clk); 115 if (ret < 0) { 116 dev_err(dev, "failed to get clock\n"); 117 return ret; 118 } 119 120 clock = clk_get_rate(&clk); 121 if (IS_ERR_VALUE(clock)) { 122 dev_err(dev, "failed to get rate\n"); 123 return clock; 124 } 125 debug("%s: CLK %ld\n", __func__, clock); 126 127 ret = clk_enable(&clk); 128 if (ret && ret != -ENOSYS) { 129 dev_err(dev, "failed to enable clock\n"); 130 return ret; 131 } 132 133 _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); 134 135 return 0; 136 } 137 138 static int zynq_serial_probe(struct udevice *dev) 139 { 140 struct zynq_uart_priv *priv = dev_get_priv(dev); 141 142 _uart_zynq_serial_init(priv->regs); 143 144 return 0; 145 } 146 147 static int zynq_serial_getc(struct udevice *dev) 148 { 149 struct zynq_uart_priv *priv = dev_get_priv(dev); 150 struct uart_zynq *regs = priv->regs; 151 152 if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) 153 return -EAGAIN; 154 155 return readl(®s->tx_rx_fifo); 156 } 157 158 static int zynq_serial_putc(struct udevice *dev, const char ch) 159 { 160 struct zynq_uart_priv *priv = dev_get_priv(dev); 161 162 return _uart_zynq_serial_putc(priv->regs, ch); 163 } 164 165 static int zynq_serial_pending(struct udevice *dev, bool input) 166 { 167 struct zynq_uart_priv *priv = dev_get_priv(dev); 168 struct uart_zynq *regs = priv->regs; 169 170 if (input) 171 return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); 172 else 173 return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); 174 } 175 176 static int zynq_serial_ofdata_to_platdata(struct udevice *dev) 177 { 178 struct zynq_uart_priv *priv = dev_get_priv(dev); 179 180 priv->regs = (struct uart_zynq *)devfdt_get_addr(dev); 181 182 return 0; 183 } 184 185 static const struct dm_serial_ops zynq_serial_ops = { 186 .putc = zynq_serial_putc, 187 .pending = zynq_serial_pending, 188 .getc = zynq_serial_getc, 189 .setbrg = zynq_serial_setbrg, 190 }; 191 192 static const struct udevice_id zynq_serial_ids[] = { 193 { .compatible = "xlnx,xuartps" }, 194 { .compatible = "cdns,uart-r1p8" }, 195 { .compatible = "cdns,uart-r1p12" }, 196 { } 197 }; 198 199 U_BOOT_DRIVER(serial_zynq) = { 200 .name = "serial_zynq", 201 .id = UCLASS_SERIAL, 202 .of_match = zynq_serial_ids, 203 .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, 204 .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), 205 .probe = zynq_serial_probe, 206 .ops = &zynq_serial_ops, 207 .flags = DM_FLAG_PRE_RELOC, 208 }; 209 210 #ifdef CONFIG_DEBUG_UART_ZYNQ 211 static inline void _debug_uart_init(void) 212 { 213 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 214 215 _uart_zynq_serial_init(regs); 216 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, 217 CONFIG_BAUDRATE); 218 } 219 220 static inline void _debug_uart_putc(int ch) 221 { 222 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 223 224 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) 225 WATCHDOG_RESET(); 226 } 227 228 DEBUG_UART_FUNCS 229 230 #endif 231