1 /* 2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <fdtdec.h> 10 #include <watchdog.h> 11 #include <asm/io.h> 12 #include <linux/compiler.h> 13 #include <serial.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/hardware.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 20 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 21 22 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 23 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 24 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 25 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 26 27 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 28 29 struct uart_zynq { 30 u32 control; /* 0x0 - Control Register [8:0] */ 31 u32 mode; /* 0x4 - Mode Register [10:0] */ 32 u32 reserved1[4]; 33 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 34 u32 reserved2[4]; 35 u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 36 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 37 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 38 }; 39 40 static struct uart_zynq *uart_zynq_ports[2] = { 41 [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, 42 [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, 43 }; 44 45 /* Set up the baud rate in gd struct */ 46 static void uart_zynq_serial_setbrg(const int port) 47 { 48 /* Calculation results. */ 49 unsigned int calc_bauderror, bdiv, bgen; 50 unsigned long calc_baud = 0; 51 unsigned long baud; 52 unsigned long clock = get_uart_clk(port); 53 struct uart_zynq *regs = uart_zynq_ports[port]; 54 55 /* Covering case where input clock is so slow */ 56 if (clock < 1000000 && gd->baudrate > 4800) 57 gd->baudrate = 4800; 58 59 baud = gd->baudrate; 60 61 /* master clock 62 * Baud rate = ------------------ 63 * bgen * (bdiv + 1) 64 * 65 * Find acceptable values for baud generation. 66 */ 67 for (bdiv = 4; bdiv < 255; bdiv++) { 68 bgen = clock / (baud * (bdiv + 1)); 69 if (bgen < 2 || bgen > 65535) 70 continue; 71 72 calc_baud = clock / (bgen * (bdiv + 1)); 73 74 /* 75 * Use first calculated baudrate with 76 * an acceptable (<3%) error 77 */ 78 if (baud > calc_baud) 79 calc_bauderror = baud - calc_baud; 80 else 81 calc_bauderror = calc_baud - baud; 82 if (((calc_bauderror * 100) / baud) < 3) 83 break; 84 } 85 86 writel(bdiv, ®s->baud_rate_divider); 87 writel(bgen, ®s->baud_rate_gen); 88 } 89 90 /* Initialize the UART, with...some settings. */ 91 static int uart_zynq_serial_init(const int port) 92 { 93 struct uart_zynq *regs = uart_zynq_ports[port]; 94 95 if (!regs) 96 return -1; 97 98 /* RX/TX enabled & reset */ 99 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 100 ZYNQ_UART_CR_RXRST, ®s->control); 101 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 102 uart_zynq_serial_setbrg(port); 103 104 return 0; 105 } 106 107 static void uart_zynq_serial_putc(const char c, const int port) 108 { 109 struct uart_zynq *regs = uart_zynq_ports[port]; 110 111 while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) 112 WATCHDOG_RESET(); 113 114 if (c == '\n') { 115 writel('\r', ®s->tx_rx_fifo); 116 while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) 117 WATCHDOG_RESET(); 118 } 119 writel(c, ®s->tx_rx_fifo); 120 } 121 122 static void uart_zynq_serial_puts(const char *s, const int port) 123 { 124 while (*s) 125 uart_zynq_serial_putc(*s++, port); 126 } 127 128 static int uart_zynq_serial_tstc(const int port) 129 { 130 struct uart_zynq *regs = uart_zynq_ports[port]; 131 132 return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; 133 } 134 135 static int uart_zynq_serial_getc(const int port) 136 { 137 struct uart_zynq *regs = uart_zynq_ports[port]; 138 139 while (!uart_zynq_serial_tstc(port)) 140 WATCHDOG_RESET(); 141 return readl(®s->tx_rx_fifo); 142 } 143 144 /* Multi serial device functions */ 145 #define DECLARE_PSSERIAL_FUNCTIONS(port) \ 146 static int uart_zynq##port##_init(void) \ 147 { return uart_zynq_serial_init(port); } \ 148 static void uart_zynq##port##_setbrg(void) \ 149 { return uart_zynq_serial_setbrg(port); } \ 150 static int uart_zynq##port##_getc(void) \ 151 { return uart_zynq_serial_getc(port); } \ 152 static int uart_zynq##port##_tstc(void) \ 153 { return uart_zynq_serial_tstc(port); } \ 154 static void uart_zynq##port##_putc(const char c) \ 155 { uart_zynq_serial_putc(c, port); } \ 156 static void uart_zynq##port##_puts(const char *s) \ 157 { uart_zynq_serial_puts(s, port); } 158 159 /* Serial device descriptor */ 160 #define INIT_PSSERIAL_STRUCTURE(port, __name) { \ 161 .name = __name, \ 162 .start = uart_zynq##port##_init, \ 163 .stop = NULL, \ 164 .setbrg = uart_zynq##port##_setbrg, \ 165 .getc = uart_zynq##port##_getc, \ 166 .tstc = uart_zynq##port##_tstc, \ 167 .putc = uart_zynq##port##_putc, \ 168 .puts = uart_zynq##port##_puts, \ 169 } 170 171 DECLARE_PSSERIAL_FUNCTIONS(0); 172 static struct serial_device uart_zynq_serial0_device = 173 INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); 174 DECLARE_PSSERIAL_FUNCTIONS(1); 175 static struct serial_device uart_zynq_serial1_device = 176 INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); 177 178 #ifdef CONFIG_OF_CONTROL 179 __weak struct serial_device *default_serial_console(void) 180 { 181 const void *blob = gd->fdt_blob; 182 int node; 183 unsigned int base_addr; 184 185 node = fdt_path_offset(blob, "serial0"); 186 if (node < 0) 187 return NULL; 188 189 base_addr = fdtdec_get_addr(blob, node, "reg"); 190 if (base_addr == FDT_ADDR_T_NONE) 191 return NULL; 192 193 if (base_addr == ZYNQ_SERIAL_BASEADDR0) 194 return &uart_zynq_serial0_device; 195 196 if (base_addr == ZYNQ_SERIAL_BASEADDR1) 197 return &uart_zynq_serial1_device; 198 199 return NULL; 200 } 201 #else 202 __weak struct serial_device *default_serial_console(void) 203 { 204 #if defined(CONFIG_ZYNQ_SERIAL_UART0) 205 if (uart_zynq_ports[0]) 206 return &uart_zynq_serial0_device; 207 #endif 208 #if defined(CONFIG_ZYNQ_SERIAL_UART1) 209 if (uart_zynq_ports[1]) 210 return &uart_zynq_serial1_device; 211 #endif 212 return NULL; 213 } 214 #endif 215 216 void zynq_serial_initialize(void) 217 { 218 serial_register(&uart_zynq_serial0_device); 219 serial_register(&uart_zynq_serial1_device); 220 } 221