183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2194846f3SMichal Simek /* 3194846f3SMichal Simek * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 4194846f3SMichal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 5194846f3SMichal Simek */ 6194846f3SMichal Simek 759da82efSMichal Simek #include <clk.h> 8194846f3SMichal Simek #include <common.h> 942800ffaSSimon Glass #include <debug_uart.h> 1042800ffaSSimon Glass #include <dm.h> 11c54c0a4cSSimon Glass #include <errno.h> 12c9416b92SMichal Simek #include <fdtdec.h> 13194846f3SMichal Simek #include <watchdog.h> 14194846f3SMichal Simek #include <asm/io.h> 15194846f3SMichal Simek #include <linux/compiler.h> 16194846f3SMichal Simek #include <serial.h> 17194846f3SMichal Simek 18*c9a2c47bSMichal Simek #define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */ 19*c9a2c47bSMichal Simek #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ 20*c9a2c47bSMichal Simek #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ 21194846f3SMichal Simek 22*c9a2c47bSMichal Simek #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ 23*c9a2c47bSMichal Simek #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */ 24*c9a2c47bSMichal Simek #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ 25*c9a2c47bSMichal Simek #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ 26194846f3SMichal Simek 27194846f3SMichal Simek #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 28194846f3SMichal Simek 29194846f3SMichal Simek struct uart_zynq { 30a2425e62SMichal Simek u32 control; /* 0x0 - Control Register [8:0] */ 31a2425e62SMichal Simek u32 mode; /* 0x4 - Mode Register [10:0] */ 32194846f3SMichal Simek u32 reserved1[4]; 33a2425e62SMichal Simek u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 34194846f3SMichal Simek u32 reserved2[4]; 35a2425e62SMichal Simek u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 36a2425e62SMichal Simek u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 37a2425e62SMichal Simek u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 38194846f3SMichal Simek }; 39194846f3SMichal Simek 4042800ffaSSimon Glass struct zynq_uart_priv { 4142800ffaSSimon Glass struct uart_zynq *regs; 42194846f3SMichal Simek }; 43194846f3SMichal Simek 44194846f3SMichal Simek /* Set up the baud rate in gd struct */ 45c54c0a4cSSimon Glass static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, 46c54c0a4cSSimon Glass unsigned long clock, unsigned long baud) 47194846f3SMichal Simek { 48194846f3SMichal Simek /* Calculation results. */ 49194846f3SMichal Simek unsigned int calc_bauderror, bdiv, bgen; 50194846f3SMichal Simek unsigned long calc_baud = 0; 51194846f3SMichal Simek 5204bc5c93SMichal Simek /* Covering case where input clock is so slow */ 53c54c0a4cSSimon Glass if (clock < 1000000 && baud > 4800) 54c54c0a4cSSimon Glass baud = 4800; 5504bc5c93SMichal Simek 56194846f3SMichal Simek /* master clock 57194846f3SMichal Simek * Baud rate = ------------------ 58194846f3SMichal Simek * bgen * (bdiv + 1) 59194846f3SMichal Simek * 60194846f3SMichal Simek * Find acceptable values for baud generation. 61194846f3SMichal Simek */ 62194846f3SMichal Simek for (bdiv = 4; bdiv < 255; bdiv++) { 63194846f3SMichal Simek bgen = clock / (baud * (bdiv + 1)); 64194846f3SMichal Simek if (bgen < 2 || bgen > 65535) 65194846f3SMichal Simek continue; 66194846f3SMichal Simek 67194846f3SMichal Simek calc_baud = clock / (bgen * (bdiv + 1)); 68194846f3SMichal Simek 69194846f3SMichal Simek /* 70194846f3SMichal Simek * Use first calculated baudrate with 71194846f3SMichal Simek * an acceptable (<3%) error 72194846f3SMichal Simek */ 73194846f3SMichal Simek if (baud > calc_baud) 74194846f3SMichal Simek calc_bauderror = baud - calc_baud; 75194846f3SMichal Simek else 76194846f3SMichal Simek calc_bauderror = calc_baud - baud; 77194846f3SMichal Simek if (((calc_bauderror * 100) / baud) < 3) 78194846f3SMichal Simek break; 79194846f3SMichal Simek } 80194846f3SMichal Simek 81194846f3SMichal Simek writel(bdiv, ®s->baud_rate_divider); 82194846f3SMichal Simek writel(bgen, ®s->baud_rate_gen); 83194846f3SMichal Simek } 84194846f3SMichal Simek 85c54c0a4cSSimon Glass /* Initialize the UART, with...some settings. */ 86c54c0a4cSSimon Glass static void _uart_zynq_serial_init(struct uart_zynq *regs) 87c54c0a4cSSimon Glass { 88c54c0a4cSSimon Glass /* RX/TX enabled & reset */ 89c54c0a4cSSimon Glass writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 90c54c0a4cSSimon Glass ZYNQ_UART_CR_RXRST, ®s->control); 91c54c0a4cSSimon Glass writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 92c54c0a4cSSimon Glass } 93c54c0a4cSSimon Glass 94c54c0a4cSSimon Glass static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) 95c54c0a4cSSimon Glass { 966cd0f2a6SMichal Simek if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) 97c54c0a4cSSimon Glass return -EAGAIN; 98c54c0a4cSSimon Glass 99c54c0a4cSSimon Glass writel(c, ®s->tx_rx_fifo); 100c54c0a4cSSimon Glass 101c54c0a4cSSimon Glass return 0; 102c54c0a4cSSimon Glass } 103c54c0a4cSSimon Glass 10442800ffaSSimon Glass int zynq_serial_setbrg(struct udevice *dev, int baudrate) 105194846f3SMichal Simek { 10642800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 10759da82efSMichal Simek unsigned long clock; 108194846f3SMichal Simek 10959da82efSMichal Simek int ret; 11059da82efSMichal Simek struct clk clk; 11159da82efSMichal Simek 11259da82efSMichal Simek ret = clk_get_by_index(dev, 0, &clk); 11359da82efSMichal Simek if (ret < 0) { 11459da82efSMichal Simek dev_err(dev, "failed to get clock\n"); 11559da82efSMichal Simek return ret; 11659da82efSMichal Simek } 11759da82efSMichal Simek 11859da82efSMichal Simek clock = clk_get_rate(&clk); 11959da82efSMichal Simek if (IS_ERR_VALUE(clock)) { 12059da82efSMichal Simek dev_err(dev, "failed to get rate\n"); 12159da82efSMichal Simek return clock; 12259da82efSMichal Simek } 12359da82efSMichal Simek debug("%s: CLK %ld\n", __func__, clock); 12459da82efSMichal Simek 12559da82efSMichal Simek ret = clk_enable(&clk); 12659da82efSMichal Simek if (ret && ret != -ENOSYS) { 12759da82efSMichal Simek dev_err(dev, "failed to enable clock\n"); 12859da82efSMichal Simek return ret; 12959da82efSMichal Simek } 130781745bdSStefan Herbrechtsmeier 13142800ffaSSimon Glass _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); 132194846f3SMichal Simek 13342800ffaSSimon Glass return 0; 134194846f3SMichal Simek } 135194846f3SMichal Simek 13642800ffaSSimon Glass static int zynq_serial_probe(struct udevice *dev) 137194846f3SMichal Simek { 13842800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 13942800ffaSSimon Glass 14042800ffaSSimon Glass _uart_zynq_serial_init(priv->regs); 14142800ffaSSimon Glass 14242800ffaSSimon Glass return 0; 143194846f3SMichal Simek } 144194846f3SMichal Simek 14542800ffaSSimon Glass static int zynq_serial_getc(struct udevice *dev) 146194846f3SMichal Simek { 14742800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 14842800ffaSSimon Glass struct uart_zynq *regs = priv->regs; 149194846f3SMichal Simek 15042800ffaSSimon Glass if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) 15142800ffaSSimon Glass return -EAGAIN; 152194846f3SMichal Simek 153194846f3SMichal Simek return readl(®s->tx_rx_fifo); 154194846f3SMichal Simek } 155194846f3SMichal Simek 15642800ffaSSimon Glass static int zynq_serial_putc(struct udevice *dev, const char ch) 157c9416b92SMichal Simek { 15842800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 159c9416b92SMichal Simek 16042800ffaSSimon Glass return _uart_zynq_serial_putc(priv->regs, ch); 161c9416b92SMichal Simek } 16251d8102fSTom Rini 16342800ffaSSimon Glass static int zynq_serial_pending(struct udevice *dev, bool input) 16451d8102fSTom Rini { 16542800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 16642800ffaSSimon Glass struct uart_zynq *regs = priv->regs; 16742800ffaSSimon Glass 16842800ffaSSimon Glass if (input) 16942800ffaSSimon Glass return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); 17042800ffaSSimon Glass else 17142800ffaSSimon Glass return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); 17251d8102fSTom Rini } 173c54c0a4cSSimon Glass 17442800ffaSSimon Glass static int zynq_serial_ofdata_to_platdata(struct udevice *dev) 17542800ffaSSimon Glass { 17642800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 17742800ffaSSimon Glass 178ce69030eSMichal Simek priv->regs = (struct uart_zynq *)dev_read_addr(dev); 179ce69030eSMichal Simek if (IS_ERR(priv->regs)) 180ce69030eSMichal Simek return PTR_ERR(priv->regs); 18142800ffaSSimon Glass 18242800ffaSSimon Glass return 0; 18342800ffaSSimon Glass } 18442800ffaSSimon Glass 18542800ffaSSimon Glass static const struct dm_serial_ops zynq_serial_ops = { 18642800ffaSSimon Glass .putc = zynq_serial_putc, 18742800ffaSSimon Glass .pending = zynq_serial_pending, 18842800ffaSSimon Glass .getc = zynq_serial_getc, 18942800ffaSSimon Glass .setbrg = zynq_serial_setbrg, 19042800ffaSSimon Glass }; 19142800ffaSSimon Glass 19242800ffaSSimon Glass static const struct udevice_id zynq_serial_ids[] = { 19342800ffaSSimon Glass { .compatible = "xlnx,xuartps" }, 19442800ffaSSimon Glass { .compatible = "cdns,uart-r1p8" }, 195a2533183SMichal Simek { .compatible = "cdns,uart-r1p12" }, 19642800ffaSSimon Glass { } 19742800ffaSSimon Glass }; 19842800ffaSSimon Glass 1996bf87dacSMichal Simek U_BOOT_DRIVER(serial_zynq) = { 20042800ffaSSimon Glass .name = "serial_zynq", 20142800ffaSSimon Glass .id = UCLASS_SERIAL, 20242800ffaSSimon Glass .of_match = zynq_serial_ids, 20342800ffaSSimon Glass .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, 20442800ffaSSimon Glass .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), 20542800ffaSSimon Glass .probe = zynq_serial_probe, 20642800ffaSSimon Glass .ops = &zynq_serial_ops, 20742800ffaSSimon Glass .flags = DM_FLAG_PRE_RELOC, 20842800ffaSSimon Glass }; 20942800ffaSSimon Glass 210c54c0a4cSSimon Glass #ifdef CONFIG_DEBUG_UART_ZYNQ 21180dc9997SMichal Simek static inline void _debug_uart_init(void) 212c54c0a4cSSimon Glass { 213c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 214c54c0a4cSSimon Glass 215c54c0a4cSSimon Glass _uart_zynq_serial_init(regs); 216c54c0a4cSSimon Glass _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, 217c54c0a4cSSimon Glass CONFIG_BAUDRATE); 218c54c0a4cSSimon Glass } 219c54c0a4cSSimon Glass 220c54c0a4cSSimon Glass static inline void _debug_uart_putc(int ch) 221c54c0a4cSSimon Glass { 222c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 223c54c0a4cSSimon Glass 224c54c0a4cSSimon Glass while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) 225c54c0a4cSSimon Glass WATCHDOG_RESET(); 226c54c0a4cSSimon Glass } 227c54c0a4cSSimon Glass 228c54c0a4cSSimon Glass DEBUG_UART_FUNCS 229c54c0a4cSSimon Glass 230c54c0a4cSSimon Glass #endif 231