1194846f3SMichal Simek /* 2194846f3SMichal Simek * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 3194846f3SMichal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 4194846f3SMichal Simek * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6194846f3SMichal Simek */ 7194846f3SMichal Simek 8194846f3SMichal Simek #include <common.h> 9*c9416b92SMichal Simek #include <fdtdec.h> 10194846f3SMichal Simek #include <watchdog.h> 11194846f3SMichal Simek #include <asm/io.h> 12194846f3SMichal Simek #include <linux/compiler.h> 13194846f3SMichal Simek #include <serial.h> 1419605e2eSSoren Brinkmann #include <asm/arch/clk.h> 15bf834950SMichal Simek #include <asm/arch/hardware.h> 16194846f3SMichal Simek 17*c9416b92SMichal Simek DECLARE_GLOBAL_DATA_PTR; 18*c9416b92SMichal Simek 19194846f3SMichal Simek #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 20194846f3SMichal Simek #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 21194846f3SMichal Simek 22194846f3SMichal Simek #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 23194846f3SMichal Simek #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 24194846f3SMichal Simek #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 25194846f3SMichal Simek #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 26194846f3SMichal Simek 27194846f3SMichal Simek #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 28194846f3SMichal Simek 29194846f3SMichal Simek struct uart_zynq { 30194846f3SMichal Simek u32 control; /* Control Register [8:0] */ 31194846f3SMichal Simek u32 mode; /* Mode Register [10:0] */ 32194846f3SMichal Simek u32 reserved1[4]; 33194846f3SMichal Simek u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ 34194846f3SMichal Simek u32 reserved2[4]; 35194846f3SMichal Simek u32 channel_sts; /* Channel Status [11:0] */ 36194846f3SMichal Simek u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ 37194846f3SMichal Simek u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ 38194846f3SMichal Simek }; 39194846f3SMichal Simek 40194846f3SMichal Simek static struct uart_zynq *uart_zynq_ports[2] = { 41bf834950SMichal Simek [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, 42bf834950SMichal Simek [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, 43194846f3SMichal Simek }; 44194846f3SMichal Simek 45bf834950SMichal Simek #if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) 46bf834950SMichal Simek # define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE 47bf834950SMichal Simek #endif 48bf834950SMichal Simek #if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) 49bf834950SMichal Simek # define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE 50bf834950SMichal Simek #endif 51bf834950SMichal Simek 52194846f3SMichal Simek struct uart_zynq_params { 53194846f3SMichal Simek u32 baudrate; 54194846f3SMichal Simek }; 55194846f3SMichal Simek 56194846f3SMichal Simek static struct uart_zynq_params uart_zynq_ports_param[2] = { 57194846f3SMichal Simek [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, 58194846f3SMichal Simek [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, 59194846f3SMichal Simek }; 60194846f3SMichal Simek 61194846f3SMichal Simek /* Set up the baud rate in gd struct */ 62194846f3SMichal Simek static void uart_zynq_serial_setbrg(const int port) 63194846f3SMichal Simek { 64194846f3SMichal Simek /* Calculation results. */ 65194846f3SMichal Simek unsigned int calc_bauderror, bdiv, bgen; 66194846f3SMichal Simek unsigned long calc_baud = 0; 67194846f3SMichal Simek unsigned long baud = uart_zynq_ports_param[port].baudrate; 6819605e2eSSoren Brinkmann unsigned long clock = get_uart_clk(port); 69194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 70194846f3SMichal Simek 71194846f3SMichal Simek /* master clock 72194846f3SMichal Simek * Baud rate = ------------------ 73194846f3SMichal Simek * bgen * (bdiv + 1) 74194846f3SMichal Simek * 75194846f3SMichal Simek * Find acceptable values for baud generation. 76194846f3SMichal Simek */ 77194846f3SMichal Simek for (bdiv = 4; bdiv < 255; bdiv++) { 78194846f3SMichal Simek bgen = clock / (baud * (bdiv + 1)); 79194846f3SMichal Simek if (bgen < 2 || bgen > 65535) 80194846f3SMichal Simek continue; 81194846f3SMichal Simek 82194846f3SMichal Simek calc_baud = clock / (bgen * (bdiv + 1)); 83194846f3SMichal Simek 84194846f3SMichal Simek /* 85194846f3SMichal Simek * Use first calculated baudrate with 86194846f3SMichal Simek * an acceptable (<3%) error 87194846f3SMichal Simek */ 88194846f3SMichal Simek if (baud > calc_baud) 89194846f3SMichal Simek calc_bauderror = baud - calc_baud; 90194846f3SMichal Simek else 91194846f3SMichal Simek calc_bauderror = calc_baud - baud; 92194846f3SMichal Simek if (((calc_bauderror * 100) / baud) < 3) 93194846f3SMichal Simek break; 94194846f3SMichal Simek } 95194846f3SMichal Simek 96194846f3SMichal Simek writel(bdiv, ®s->baud_rate_divider); 97194846f3SMichal Simek writel(bgen, ®s->baud_rate_gen); 98194846f3SMichal Simek } 99194846f3SMichal Simek 100194846f3SMichal Simek /* Initialize the UART, with...some settings. */ 101194846f3SMichal Simek static int uart_zynq_serial_init(const int port) 102194846f3SMichal Simek { 103194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 104194846f3SMichal Simek 105194846f3SMichal Simek if (!regs) 106194846f3SMichal Simek return -1; 107194846f3SMichal Simek 108194846f3SMichal Simek /* RX/TX enabled & reset */ 109194846f3SMichal Simek writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 110194846f3SMichal Simek ZYNQ_UART_CR_RXRST, ®s->control); 111194846f3SMichal Simek writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 112194846f3SMichal Simek uart_zynq_serial_setbrg(port); 113194846f3SMichal Simek 114194846f3SMichal Simek return 0; 115194846f3SMichal Simek } 116194846f3SMichal Simek 117194846f3SMichal Simek static void uart_zynq_serial_putc(const char c, const int port) 118194846f3SMichal Simek { 119194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 120194846f3SMichal Simek 121194846f3SMichal Simek while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) 122194846f3SMichal Simek WATCHDOG_RESET(); 123194846f3SMichal Simek 124194846f3SMichal Simek if (c == '\n') { 125194846f3SMichal Simek writel('\r', ®s->tx_rx_fifo); 126194846f3SMichal Simek while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) 127194846f3SMichal Simek WATCHDOG_RESET(); 128194846f3SMichal Simek } 129194846f3SMichal Simek writel(c, ®s->tx_rx_fifo); 130194846f3SMichal Simek } 131194846f3SMichal Simek 132194846f3SMichal Simek static void uart_zynq_serial_puts(const char *s, const int port) 133194846f3SMichal Simek { 134194846f3SMichal Simek while (*s) 135194846f3SMichal Simek uart_zynq_serial_putc(*s++, port); 136194846f3SMichal Simek } 137194846f3SMichal Simek 138194846f3SMichal Simek static int uart_zynq_serial_tstc(const int port) 139194846f3SMichal Simek { 140194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 141194846f3SMichal Simek 142194846f3SMichal Simek return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; 143194846f3SMichal Simek } 144194846f3SMichal Simek 145194846f3SMichal Simek static int uart_zynq_serial_getc(const int port) 146194846f3SMichal Simek { 147194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 148194846f3SMichal Simek 149194846f3SMichal Simek while (!uart_zynq_serial_tstc(port)) 150194846f3SMichal Simek WATCHDOG_RESET(); 151194846f3SMichal Simek return readl(®s->tx_rx_fifo); 152194846f3SMichal Simek } 153194846f3SMichal Simek 154194846f3SMichal Simek /* Multi serial device functions */ 155194846f3SMichal Simek #define DECLARE_PSSERIAL_FUNCTIONS(port) \ 156194846f3SMichal Simek int uart_zynq##port##_init(void) \ 157194846f3SMichal Simek { return uart_zynq_serial_init(port); } \ 158194846f3SMichal Simek void uart_zynq##port##_setbrg(void) \ 159194846f3SMichal Simek { return uart_zynq_serial_setbrg(port); } \ 160194846f3SMichal Simek int uart_zynq##port##_getc(void) \ 161194846f3SMichal Simek { return uart_zynq_serial_getc(port); } \ 162194846f3SMichal Simek int uart_zynq##port##_tstc(void) \ 163194846f3SMichal Simek { return uart_zynq_serial_tstc(port); } \ 164194846f3SMichal Simek void uart_zynq##port##_putc(const char c) \ 165194846f3SMichal Simek { uart_zynq_serial_putc(c, port); } \ 166194846f3SMichal Simek void uart_zynq##port##_puts(const char *s) \ 167194846f3SMichal Simek { uart_zynq_serial_puts(s, port); } 168194846f3SMichal Simek 169194846f3SMichal Simek /* Serial device descriptor */ 170194846f3SMichal Simek #define INIT_PSSERIAL_STRUCTURE(port, __name) { \ 171194846f3SMichal Simek .name = __name, \ 17289143fb3SMarek Vasut .start = uart_zynq##port##_init, \ 17389143fb3SMarek Vasut .stop = NULL, \ 174194846f3SMichal Simek .setbrg = uart_zynq##port##_setbrg, \ 175194846f3SMichal Simek .getc = uart_zynq##port##_getc, \ 176194846f3SMichal Simek .tstc = uart_zynq##port##_tstc, \ 177194846f3SMichal Simek .putc = uart_zynq##port##_putc, \ 178194846f3SMichal Simek .puts = uart_zynq##port##_puts, \ 179194846f3SMichal Simek } 180194846f3SMichal Simek 181194846f3SMichal Simek DECLARE_PSSERIAL_FUNCTIONS(0); 182194846f3SMichal Simek struct serial_device uart_zynq_serial0_device = 183194846f3SMichal Simek INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); 184194846f3SMichal Simek DECLARE_PSSERIAL_FUNCTIONS(1); 185194846f3SMichal Simek struct serial_device uart_zynq_serial1_device = 186194846f3SMichal Simek INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); 187194846f3SMichal Simek 188*c9416b92SMichal Simek #ifdef CONFIG_OF_CONTROL 189*c9416b92SMichal Simek __weak struct serial_device *default_serial_console(void) 190*c9416b92SMichal Simek { 191*c9416b92SMichal Simek const void *blob = gd->fdt_blob; 192*c9416b92SMichal Simek int node; 193*c9416b92SMichal Simek unsigned int base_addr; 194*c9416b92SMichal Simek 195*c9416b92SMichal Simek node = fdt_path_offset(blob, "serial0"); 196*c9416b92SMichal Simek if (node < 0) 197*c9416b92SMichal Simek return NULL; 198*c9416b92SMichal Simek 199*c9416b92SMichal Simek base_addr = fdtdec_get_addr(blob, node, "reg"); 200*c9416b92SMichal Simek if (base_addr == FDT_ADDR_T_NONE) 201*c9416b92SMichal Simek return NULL; 202*c9416b92SMichal Simek 203*c9416b92SMichal Simek if (base_addr == ZYNQ_SERIAL_BASEADDR0) 204*c9416b92SMichal Simek return &uart_zynq_serial0_device; 205*c9416b92SMichal Simek 206*c9416b92SMichal Simek if (base_addr == ZYNQ_SERIAL_BASEADDR1) 207*c9416b92SMichal Simek return &uart_zynq_serial1_device; 208*c9416b92SMichal Simek 209*c9416b92SMichal Simek return NULL; 210*c9416b92SMichal Simek } 211*c9416b92SMichal Simek #else 212194846f3SMichal Simek __weak struct serial_device *default_serial_console(void) 213194846f3SMichal Simek { 214bf834950SMichal Simek #if defined(CONFIG_ZYNQ_SERIAL_UART0) 215194846f3SMichal Simek if (uart_zynq_ports[0]) 216194846f3SMichal Simek return &uart_zynq_serial0_device; 217bf834950SMichal Simek #endif 218bf834950SMichal Simek #if defined(CONFIG_ZYNQ_SERIAL_UART1) 219194846f3SMichal Simek if (uart_zynq_ports[1]) 220194846f3SMichal Simek return &uart_zynq_serial1_device; 221bf834950SMichal Simek #endif 222194846f3SMichal Simek return NULL; 223194846f3SMichal Simek } 224*c9416b92SMichal Simek #endif 22551d8102fSTom Rini 22651d8102fSTom Rini void zynq_serial_initalize(void) 22751d8102fSTom Rini { 22851d8102fSTom Rini serial_register(&uart_zynq_serial0_device); 22951d8102fSTom Rini serial_register(&uart_zynq_serial1_device); 23051d8102fSTom Rini } 231