1194846f3SMichal Simek /* 2194846f3SMichal Simek * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 3194846f3SMichal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 4194846f3SMichal Simek * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6194846f3SMichal Simek */ 7194846f3SMichal Simek 8194846f3SMichal Simek #include <common.h> 9*c54c0a4cSSimon Glass #include <errno.h> 10c9416b92SMichal Simek #include <fdtdec.h> 11194846f3SMichal Simek #include <watchdog.h> 12194846f3SMichal Simek #include <asm/io.h> 13194846f3SMichal Simek #include <linux/compiler.h> 14194846f3SMichal Simek #include <serial.h> 1519605e2eSSoren Brinkmann #include <asm/arch/clk.h> 16bf834950SMichal Simek #include <asm/arch/hardware.h> 17194846f3SMichal Simek 18c9416b92SMichal Simek DECLARE_GLOBAL_DATA_PTR; 19c9416b92SMichal Simek 20194846f3SMichal Simek #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 21194846f3SMichal Simek #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 22194846f3SMichal Simek 23194846f3SMichal Simek #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 24194846f3SMichal Simek #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 25194846f3SMichal Simek #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 26194846f3SMichal Simek #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 27194846f3SMichal Simek 28194846f3SMichal Simek #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 29194846f3SMichal Simek 30194846f3SMichal Simek struct uart_zynq { 31a2425e62SMichal Simek u32 control; /* 0x0 - Control Register [8:0] */ 32a2425e62SMichal Simek u32 mode; /* 0x4 - Mode Register [10:0] */ 33194846f3SMichal Simek u32 reserved1[4]; 34a2425e62SMichal Simek u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 35194846f3SMichal Simek u32 reserved2[4]; 36a2425e62SMichal Simek u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 37a2425e62SMichal Simek u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 38a2425e62SMichal Simek u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 39194846f3SMichal Simek }; 40194846f3SMichal Simek 41194846f3SMichal Simek static struct uart_zynq *uart_zynq_ports[2] = { 42bf834950SMichal Simek [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, 43bf834950SMichal Simek [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, 44194846f3SMichal Simek }; 45194846f3SMichal Simek 46194846f3SMichal Simek /* Set up the baud rate in gd struct */ 47*c54c0a4cSSimon Glass static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, 48*c54c0a4cSSimon Glass unsigned long clock, unsigned long baud) 49194846f3SMichal Simek { 50194846f3SMichal Simek /* Calculation results. */ 51194846f3SMichal Simek unsigned int calc_bauderror, bdiv, bgen; 52194846f3SMichal Simek unsigned long calc_baud = 0; 53194846f3SMichal Simek 5404bc5c93SMichal Simek /* Covering case where input clock is so slow */ 55*c54c0a4cSSimon Glass if (clock < 1000000 && baud > 4800) 56*c54c0a4cSSimon Glass baud = 4800; 5704bc5c93SMichal Simek 58194846f3SMichal Simek /* master clock 59194846f3SMichal Simek * Baud rate = ------------------ 60194846f3SMichal Simek * bgen * (bdiv + 1) 61194846f3SMichal Simek * 62194846f3SMichal Simek * Find acceptable values for baud generation. 63194846f3SMichal Simek */ 64194846f3SMichal Simek for (bdiv = 4; bdiv < 255; bdiv++) { 65194846f3SMichal Simek bgen = clock / (baud * (bdiv + 1)); 66194846f3SMichal Simek if (bgen < 2 || bgen > 65535) 67194846f3SMichal Simek continue; 68194846f3SMichal Simek 69194846f3SMichal Simek calc_baud = clock / (bgen * (bdiv + 1)); 70194846f3SMichal Simek 71194846f3SMichal Simek /* 72194846f3SMichal Simek * Use first calculated baudrate with 73194846f3SMichal Simek * an acceptable (<3%) error 74194846f3SMichal Simek */ 75194846f3SMichal Simek if (baud > calc_baud) 76194846f3SMichal Simek calc_bauderror = baud - calc_baud; 77194846f3SMichal Simek else 78194846f3SMichal Simek calc_bauderror = calc_baud - baud; 79194846f3SMichal Simek if (((calc_bauderror * 100) / baud) < 3) 80194846f3SMichal Simek break; 81194846f3SMichal Simek } 82194846f3SMichal Simek 83194846f3SMichal Simek writel(bdiv, ®s->baud_rate_divider); 84194846f3SMichal Simek writel(bgen, ®s->baud_rate_gen); 85194846f3SMichal Simek } 86194846f3SMichal Simek 87*c54c0a4cSSimon Glass /* Set up the baud rate in gd struct */ 88*c54c0a4cSSimon Glass static void uart_zynq_serial_setbrg(const int port) 89*c54c0a4cSSimon Glass { 90*c54c0a4cSSimon Glass unsigned long clock = get_uart_clk(port); 91*c54c0a4cSSimon Glass struct uart_zynq *regs = uart_zynq_ports[port]; 92*c54c0a4cSSimon Glass 93*c54c0a4cSSimon Glass return _uart_zynq_serial_setbrg(regs, clock, gd->baudrate); 94*c54c0a4cSSimon Glass } 95*c54c0a4cSSimon Glass 96*c54c0a4cSSimon Glass /* Initialize the UART, with...some settings. */ 97*c54c0a4cSSimon Glass static void _uart_zynq_serial_init(struct uart_zynq *regs) 98*c54c0a4cSSimon Glass { 99*c54c0a4cSSimon Glass /* RX/TX enabled & reset */ 100*c54c0a4cSSimon Glass writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 101*c54c0a4cSSimon Glass ZYNQ_UART_CR_RXRST, ®s->control); 102*c54c0a4cSSimon Glass writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 103*c54c0a4cSSimon Glass } 104*c54c0a4cSSimon Glass 105194846f3SMichal Simek /* Initialize the UART, with...some settings. */ 106194846f3SMichal Simek static int uart_zynq_serial_init(const int port) 107194846f3SMichal Simek { 108194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 109194846f3SMichal Simek 110194846f3SMichal Simek if (!regs) 111194846f3SMichal Simek return -1; 112194846f3SMichal Simek 113*c54c0a4cSSimon Glass _uart_zynq_serial_init(regs); 114194846f3SMichal Simek uart_zynq_serial_setbrg(port); 115194846f3SMichal Simek 116194846f3SMichal Simek return 0; 117194846f3SMichal Simek } 118194846f3SMichal Simek 119*c54c0a4cSSimon Glass static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) 120*c54c0a4cSSimon Glass { 121*c54c0a4cSSimon Glass if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) 122*c54c0a4cSSimon Glass return -EAGAIN; 123*c54c0a4cSSimon Glass 124*c54c0a4cSSimon Glass writel(c, ®s->tx_rx_fifo); 125*c54c0a4cSSimon Glass 126*c54c0a4cSSimon Glass return 0; 127*c54c0a4cSSimon Glass } 128*c54c0a4cSSimon Glass 129194846f3SMichal Simek static void uart_zynq_serial_putc(const char c, const int port) 130194846f3SMichal Simek { 131194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 132194846f3SMichal Simek 133*c54c0a4cSSimon Glass while (_uart_zynq_serial_putc(regs, c) == -EAGAIN) 134194846f3SMichal Simek WATCHDOG_RESET(); 135194846f3SMichal Simek 136194846f3SMichal Simek if (c == '\n') { 137*c54c0a4cSSimon Glass while (_uart_zynq_serial_putc(regs, '\r') == -EAGAIN) 138194846f3SMichal Simek WATCHDOG_RESET(); 139194846f3SMichal Simek } 140194846f3SMichal Simek } 141194846f3SMichal Simek 142194846f3SMichal Simek static void uart_zynq_serial_puts(const char *s, const int port) 143194846f3SMichal Simek { 144194846f3SMichal Simek while (*s) 145194846f3SMichal Simek uart_zynq_serial_putc(*s++, port); 146194846f3SMichal Simek } 147194846f3SMichal Simek 148194846f3SMichal Simek static int uart_zynq_serial_tstc(const int port) 149194846f3SMichal Simek { 150194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 151194846f3SMichal Simek 152194846f3SMichal Simek return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; 153194846f3SMichal Simek } 154194846f3SMichal Simek 155194846f3SMichal Simek static int uart_zynq_serial_getc(const int port) 156194846f3SMichal Simek { 157194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 158194846f3SMichal Simek 159194846f3SMichal Simek while (!uart_zynq_serial_tstc(port)) 160194846f3SMichal Simek WATCHDOG_RESET(); 161194846f3SMichal Simek return readl(®s->tx_rx_fifo); 162194846f3SMichal Simek } 163194846f3SMichal Simek 164194846f3SMichal Simek /* Multi serial device functions */ 165194846f3SMichal Simek #define DECLARE_PSSERIAL_FUNCTIONS(port) \ 1666c4da359SMichal Simek static int uart_zynq##port##_init(void) \ 167194846f3SMichal Simek { return uart_zynq_serial_init(port); } \ 1686c4da359SMichal Simek static void uart_zynq##port##_setbrg(void) \ 169194846f3SMichal Simek { return uart_zynq_serial_setbrg(port); } \ 1706c4da359SMichal Simek static int uart_zynq##port##_getc(void) \ 171194846f3SMichal Simek { return uart_zynq_serial_getc(port); } \ 1726c4da359SMichal Simek static int uart_zynq##port##_tstc(void) \ 173194846f3SMichal Simek { return uart_zynq_serial_tstc(port); } \ 1746c4da359SMichal Simek static void uart_zynq##port##_putc(const char c) \ 175194846f3SMichal Simek { uart_zynq_serial_putc(c, port); } \ 1766c4da359SMichal Simek static void uart_zynq##port##_puts(const char *s) \ 177194846f3SMichal Simek { uart_zynq_serial_puts(s, port); } 178194846f3SMichal Simek 179194846f3SMichal Simek /* Serial device descriptor */ 180194846f3SMichal Simek #define INIT_PSSERIAL_STRUCTURE(port, __name) { \ 181194846f3SMichal Simek .name = __name, \ 18289143fb3SMarek Vasut .start = uart_zynq##port##_init, \ 18389143fb3SMarek Vasut .stop = NULL, \ 184194846f3SMichal Simek .setbrg = uart_zynq##port##_setbrg, \ 185194846f3SMichal Simek .getc = uart_zynq##port##_getc, \ 186194846f3SMichal Simek .tstc = uart_zynq##port##_tstc, \ 187194846f3SMichal Simek .putc = uart_zynq##port##_putc, \ 188194846f3SMichal Simek .puts = uart_zynq##port##_puts, \ 189194846f3SMichal Simek } 190194846f3SMichal Simek 191194846f3SMichal Simek DECLARE_PSSERIAL_FUNCTIONS(0); 1926c4da359SMichal Simek static struct serial_device uart_zynq_serial0_device = 193194846f3SMichal Simek INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); 194194846f3SMichal Simek DECLARE_PSSERIAL_FUNCTIONS(1); 1956c4da359SMichal Simek static struct serial_device uart_zynq_serial1_device = 196194846f3SMichal Simek INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); 197194846f3SMichal Simek 1980f925822SMasahiro Yamada #if CONFIG_IS_ENABLED(OF_CONTROL) 199c9416b92SMichal Simek __weak struct serial_device *default_serial_console(void) 200c9416b92SMichal Simek { 201c9416b92SMichal Simek const void *blob = gd->fdt_blob; 202c9416b92SMichal Simek int node; 203c9416b92SMichal Simek unsigned int base_addr; 204c9416b92SMichal Simek 205c9416b92SMichal Simek node = fdt_path_offset(blob, "serial0"); 206c9416b92SMichal Simek if (node < 0) 207c9416b92SMichal Simek return NULL; 208c9416b92SMichal Simek 209c9416b92SMichal Simek base_addr = fdtdec_get_addr(blob, node, "reg"); 210c9416b92SMichal Simek if (base_addr == FDT_ADDR_T_NONE) 211c9416b92SMichal Simek return NULL; 212c9416b92SMichal Simek 213c9416b92SMichal Simek if (base_addr == ZYNQ_SERIAL_BASEADDR0) 214c9416b92SMichal Simek return &uart_zynq_serial0_device; 215c9416b92SMichal Simek 216c9416b92SMichal Simek if (base_addr == ZYNQ_SERIAL_BASEADDR1) 217c9416b92SMichal Simek return &uart_zynq_serial1_device; 218c9416b92SMichal Simek 219c9416b92SMichal Simek return NULL; 220c9416b92SMichal Simek } 221c9416b92SMichal Simek #else 222194846f3SMichal Simek __weak struct serial_device *default_serial_console(void) 223194846f3SMichal Simek { 224bf834950SMichal Simek #if defined(CONFIG_ZYNQ_SERIAL_UART0) 225194846f3SMichal Simek if (uart_zynq_ports[0]) 226194846f3SMichal Simek return &uart_zynq_serial0_device; 227bf834950SMichal Simek #endif 228bf834950SMichal Simek #if defined(CONFIG_ZYNQ_SERIAL_UART1) 229194846f3SMichal Simek if (uart_zynq_ports[1]) 230194846f3SMichal Simek return &uart_zynq_serial1_device; 231bf834950SMichal Simek #endif 232194846f3SMichal Simek return NULL; 233194846f3SMichal Simek } 234c9416b92SMichal Simek #endif 23551d8102fSTom Rini 236870e0bdaSMichal Simek void zynq_serial_initialize(void) 23751d8102fSTom Rini { 23851d8102fSTom Rini serial_register(&uart_zynq_serial0_device); 23951d8102fSTom Rini serial_register(&uart_zynq_serial1_device); 24051d8102fSTom Rini } 241*c54c0a4cSSimon Glass 242*c54c0a4cSSimon Glass #ifdef CONFIG_DEBUG_UART_ZYNQ 243*c54c0a4cSSimon Glass 244*c54c0a4cSSimon Glass #include <debug_uart.h> 245*c54c0a4cSSimon Glass 246*c54c0a4cSSimon Glass void _debug_uart_init(void) 247*c54c0a4cSSimon Glass { 248*c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 249*c54c0a4cSSimon Glass 250*c54c0a4cSSimon Glass _uart_zynq_serial_init(regs); 251*c54c0a4cSSimon Glass _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, 252*c54c0a4cSSimon Glass CONFIG_BAUDRATE); 253*c54c0a4cSSimon Glass } 254*c54c0a4cSSimon Glass 255*c54c0a4cSSimon Glass static inline void _debug_uart_putc(int ch) 256*c54c0a4cSSimon Glass { 257*c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 258*c54c0a4cSSimon Glass 259*c54c0a4cSSimon Glass while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) 260*c54c0a4cSSimon Glass WATCHDOG_RESET(); 261*c54c0a4cSSimon Glass } 262*c54c0a4cSSimon Glass 263*c54c0a4cSSimon Glass DEBUG_UART_FUNCS 264*c54c0a4cSSimon Glass 265*c54c0a4cSSimon Glass #endif 266