1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2194846f3SMichal Simek /* 3194846f3SMichal Simek * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 4194846f3SMichal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 5194846f3SMichal Simek */ 6194846f3SMichal Simek 759da82efSMichal Simek #include <clk.h> 8194846f3SMichal Simek #include <common.h> 942800ffaSSimon Glass #include <debug_uart.h> 1042800ffaSSimon Glass #include <dm.h> 11c54c0a4cSSimon Glass #include <errno.h> 12c9416b92SMichal Simek #include <fdtdec.h> 13194846f3SMichal Simek #include <watchdog.h> 14194846f3SMichal Simek #include <asm/io.h> 15194846f3SMichal Simek #include <linux/compiler.h> 16194846f3SMichal Simek #include <serial.h> 17bf834950SMichal Simek #include <asm/arch/hardware.h> 18194846f3SMichal Simek 196cd0f2a6SMichal Simek #define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ 2042800ffaSSimon Glass #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ 21194846f3SMichal Simek #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 22194846f3SMichal Simek 23194846f3SMichal Simek #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 24194846f3SMichal Simek #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 25194846f3SMichal Simek #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 26194846f3SMichal Simek #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 27194846f3SMichal Simek 28194846f3SMichal Simek #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 29194846f3SMichal Simek 30194846f3SMichal Simek struct uart_zynq { 31a2425e62SMichal Simek u32 control; /* 0x0 - Control Register [8:0] */ 32a2425e62SMichal Simek u32 mode; /* 0x4 - Mode Register [10:0] */ 33194846f3SMichal Simek u32 reserved1[4]; 34a2425e62SMichal Simek u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 35194846f3SMichal Simek u32 reserved2[4]; 36a2425e62SMichal Simek u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 37a2425e62SMichal Simek u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 38a2425e62SMichal Simek u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 39194846f3SMichal Simek }; 40194846f3SMichal Simek 4142800ffaSSimon Glass struct zynq_uart_priv { 4242800ffaSSimon Glass struct uart_zynq *regs; 43194846f3SMichal Simek }; 44194846f3SMichal Simek 45194846f3SMichal Simek /* Set up the baud rate in gd struct */ 46c54c0a4cSSimon Glass static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, 47c54c0a4cSSimon Glass unsigned long clock, unsigned long baud) 48194846f3SMichal Simek { 49194846f3SMichal Simek /* Calculation results. */ 50194846f3SMichal Simek unsigned int calc_bauderror, bdiv, bgen; 51194846f3SMichal Simek unsigned long calc_baud = 0; 52194846f3SMichal Simek 5304bc5c93SMichal Simek /* Covering case where input clock is so slow */ 54c54c0a4cSSimon Glass if (clock < 1000000 && baud > 4800) 55c54c0a4cSSimon Glass baud = 4800; 5604bc5c93SMichal Simek 57194846f3SMichal Simek /* master clock 58194846f3SMichal Simek * Baud rate = ------------------ 59194846f3SMichal Simek * bgen * (bdiv + 1) 60194846f3SMichal Simek * 61194846f3SMichal Simek * Find acceptable values for baud generation. 62194846f3SMichal Simek */ 63194846f3SMichal Simek for (bdiv = 4; bdiv < 255; bdiv++) { 64194846f3SMichal Simek bgen = clock / (baud * (bdiv + 1)); 65194846f3SMichal Simek if (bgen < 2 || bgen > 65535) 66194846f3SMichal Simek continue; 67194846f3SMichal Simek 68194846f3SMichal Simek calc_baud = clock / (bgen * (bdiv + 1)); 69194846f3SMichal Simek 70194846f3SMichal Simek /* 71194846f3SMichal Simek * Use first calculated baudrate with 72194846f3SMichal Simek * an acceptable (<3%) error 73194846f3SMichal Simek */ 74194846f3SMichal Simek if (baud > calc_baud) 75194846f3SMichal Simek calc_bauderror = baud - calc_baud; 76194846f3SMichal Simek else 77194846f3SMichal Simek calc_bauderror = calc_baud - baud; 78194846f3SMichal Simek if (((calc_bauderror * 100) / baud) < 3) 79194846f3SMichal Simek break; 80194846f3SMichal Simek } 81194846f3SMichal Simek 82194846f3SMichal Simek writel(bdiv, ®s->baud_rate_divider); 83194846f3SMichal Simek writel(bgen, ®s->baud_rate_gen); 84194846f3SMichal Simek } 85194846f3SMichal Simek 86c54c0a4cSSimon Glass /* Initialize the UART, with...some settings. */ 87c54c0a4cSSimon Glass static void _uart_zynq_serial_init(struct uart_zynq *regs) 88c54c0a4cSSimon Glass { 89c54c0a4cSSimon Glass /* RX/TX enabled & reset */ 90c54c0a4cSSimon Glass writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 91c54c0a4cSSimon Glass ZYNQ_UART_CR_RXRST, ®s->control); 92c54c0a4cSSimon Glass writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 93c54c0a4cSSimon Glass } 94c54c0a4cSSimon Glass 95c54c0a4cSSimon Glass static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) 96c54c0a4cSSimon Glass { 976cd0f2a6SMichal Simek if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) 98c54c0a4cSSimon Glass return -EAGAIN; 99c54c0a4cSSimon Glass 100c54c0a4cSSimon Glass writel(c, ®s->tx_rx_fifo); 101c54c0a4cSSimon Glass 102c54c0a4cSSimon Glass return 0; 103c54c0a4cSSimon Glass } 104c54c0a4cSSimon Glass 10542800ffaSSimon Glass int zynq_serial_setbrg(struct udevice *dev, int baudrate) 106194846f3SMichal Simek { 10742800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 10859da82efSMichal Simek unsigned long clock; 109194846f3SMichal Simek 11059da82efSMichal Simek int ret; 11159da82efSMichal Simek struct clk clk; 11259da82efSMichal Simek 11359da82efSMichal Simek ret = clk_get_by_index(dev, 0, &clk); 11459da82efSMichal Simek if (ret < 0) { 11559da82efSMichal Simek dev_err(dev, "failed to get clock\n"); 11659da82efSMichal Simek return ret; 11759da82efSMichal Simek } 11859da82efSMichal Simek 11959da82efSMichal Simek clock = clk_get_rate(&clk); 12059da82efSMichal Simek if (IS_ERR_VALUE(clock)) { 12159da82efSMichal Simek dev_err(dev, "failed to get rate\n"); 12259da82efSMichal Simek return clock; 12359da82efSMichal Simek } 12459da82efSMichal Simek debug("%s: CLK %ld\n", __func__, clock); 12559da82efSMichal Simek 12659da82efSMichal Simek ret = clk_enable(&clk); 12759da82efSMichal Simek if (ret && ret != -ENOSYS) { 12859da82efSMichal Simek dev_err(dev, "failed to enable clock\n"); 12959da82efSMichal Simek return ret; 13059da82efSMichal Simek } 131781745bdSStefan Herbrechtsmeier 13242800ffaSSimon Glass _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); 133194846f3SMichal Simek 13442800ffaSSimon Glass return 0; 135194846f3SMichal Simek } 136194846f3SMichal Simek 13742800ffaSSimon Glass static int zynq_serial_probe(struct udevice *dev) 138194846f3SMichal Simek { 13942800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 14042800ffaSSimon Glass 14142800ffaSSimon Glass _uart_zynq_serial_init(priv->regs); 14242800ffaSSimon Glass 14342800ffaSSimon Glass return 0; 144194846f3SMichal Simek } 145194846f3SMichal Simek 14642800ffaSSimon Glass static int zynq_serial_getc(struct udevice *dev) 147194846f3SMichal Simek { 14842800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 14942800ffaSSimon Glass struct uart_zynq *regs = priv->regs; 150194846f3SMichal Simek 15142800ffaSSimon Glass if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) 15242800ffaSSimon Glass return -EAGAIN; 153194846f3SMichal Simek 154194846f3SMichal Simek return readl(®s->tx_rx_fifo); 155194846f3SMichal Simek } 156194846f3SMichal Simek 15742800ffaSSimon Glass static int zynq_serial_putc(struct udevice *dev, const char ch) 158c9416b92SMichal Simek { 15942800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 160c9416b92SMichal Simek 16142800ffaSSimon Glass return _uart_zynq_serial_putc(priv->regs, ch); 162c9416b92SMichal Simek } 16351d8102fSTom Rini 16442800ffaSSimon Glass static int zynq_serial_pending(struct udevice *dev, bool input) 16551d8102fSTom Rini { 16642800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 16742800ffaSSimon Glass struct uart_zynq *regs = priv->regs; 16842800ffaSSimon Glass 16942800ffaSSimon Glass if (input) 17042800ffaSSimon Glass return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); 17142800ffaSSimon Glass else 17242800ffaSSimon Glass return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); 17351d8102fSTom Rini } 174c54c0a4cSSimon Glass 17542800ffaSSimon Glass static int zynq_serial_ofdata_to_platdata(struct udevice *dev) 17642800ffaSSimon Glass { 17742800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 17842800ffaSSimon Glass 179a821c4afSSimon Glass priv->regs = (struct uart_zynq *)devfdt_get_addr(dev); 18042800ffaSSimon Glass 18142800ffaSSimon Glass return 0; 18242800ffaSSimon Glass } 18342800ffaSSimon Glass 18442800ffaSSimon Glass static const struct dm_serial_ops zynq_serial_ops = { 18542800ffaSSimon Glass .putc = zynq_serial_putc, 18642800ffaSSimon Glass .pending = zynq_serial_pending, 18742800ffaSSimon Glass .getc = zynq_serial_getc, 18842800ffaSSimon Glass .setbrg = zynq_serial_setbrg, 18942800ffaSSimon Glass }; 19042800ffaSSimon Glass 19142800ffaSSimon Glass static const struct udevice_id zynq_serial_ids[] = { 19242800ffaSSimon Glass { .compatible = "xlnx,xuartps" }, 19342800ffaSSimon Glass { .compatible = "cdns,uart-r1p8" }, 194a2533183SMichal Simek { .compatible = "cdns,uart-r1p12" }, 19542800ffaSSimon Glass { } 19642800ffaSSimon Glass }; 19742800ffaSSimon Glass 1986bf87dacSMichal Simek U_BOOT_DRIVER(serial_zynq) = { 19942800ffaSSimon Glass .name = "serial_zynq", 20042800ffaSSimon Glass .id = UCLASS_SERIAL, 20142800ffaSSimon Glass .of_match = zynq_serial_ids, 20242800ffaSSimon Glass .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, 20342800ffaSSimon Glass .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), 20442800ffaSSimon Glass .probe = zynq_serial_probe, 20542800ffaSSimon Glass .ops = &zynq_serial_ops, 20642800ffaSSimon Glass .flags = DM_FLAG_PRE_RELOC, 20742800ffaSSimon Glass }; 20842800ffaSSimon Glass 209c54c0a4cSSimon Glass #ifdef CONFIG_DEBUG_UART_ZYNQ 21080dc9997SMichal Simek static inline void _debug_uart_init(void) 211c54c0a4cSSimon Glass { 212c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 213c54c0a4cSSimon Glass 214c54c0a4cSSimon Glass _uart_zynq_serial_init(regs); 215c54c0a4cSSimon Glass _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, 216c54c0a4cSSimon Glass CONFIG_BAUDRATE); 217c54c0a4cSSimon Glass } 218c54c0a4cSSimon Glass 219c54c0a4cSSimon Glass static inline void _debug_uart_putc(int ch) 220c54c0a4cSSimon Glass { 221c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 222c54c0a4cSSimon Glass 223c54c0a4cSSimon Glass while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) 224c54c0a4cSSimon Glass WATCHDOG_RESET(); 225c54c0a4cSSimon Glass } 226c54c0a4cSSimon Glass 227c54c0a4cSSimon Glass DEBUG_UART_FUNCS 228c54c0a4cSSimon Glass 229c54c0a4cSSimon Glass #endif 230