1194846f3SMichal Simek /* 2194846f3SMichal Simek * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 3194846f3SMichal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 4194846f3SMichal Simek * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6194846f3SMichal Simek */ 7194846f3SMichal Simek 859da82efSMichal Simek #include <clk.h> 9194846f3SMichal Simek #include <common.h> 1042800ffaSSimon Glass #include <debug_uart.h> 1142800ffaSSimon Glass #include <dm.h> 12c54c0a4cSSimon Glass #include <errno.h> 13c9416b92SMichal Simek #include <fdtdec.h> 14194846f3SMichal Simek #include <watchdog.h> 15194846f3SMichal Simek #include <asm/io.h> 16194846f3SMichal Simek #include <linux/compiler.h> 17194846f3SMichal Simek #include <serial.h> 18bf834950SMichal Simek #include <asm/arch/hardware.h> 19194846f3SMichal Simek 20c9416b92SMichal Simek DECLARE_GLOBAL_DATA_PTR; 21c9416b92SMichal Simek 226cd0f2a6SMichal Simek #define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ 2342800ffaSSimon Glass #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ 24194846f3SMichal Simek #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 25194846f3SMichal Simek 26194846f3SMichal Simek #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 27194846f3SMichal Simek #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 28194846f3SMichal Simek #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 29194846f3SMichal Simek #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 30194846f3SMichal Simek 31194846f3SMichal Simek #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 32194846f3SMichal Simek 33194846f3SMichal Simek struct uart_zynq { 34a2425e62SMichal Simek u32 control; /* 0x0 - Control Register [8:0] */ 35a2425e62SMichal Simek u32 mode; /* 0x4 - Mode Register [10:0] */ 36194846f3SMichal Simek u32 reserved1[4]; 37a2425e62SMichal Simek u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ 38194846f3SMichal Simek u32 reserved2[4]; 39a2425e62SMichal Simek u32 channel_sts; /* 0x2c - Channel Status [11:0] */ 40a2425e62SMichal Simek u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ 41a2425e62SMichal Simek u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ 42194846f3SMichal Simek }; 43194846f3SMichal Simek 4442800ffaSSimon Glass struct zynq_uart_priv { 4542800ffaSSimon Glass struct uart_zynq *regs; 46194846f3SMichal Simek }; 47194846f3SMichal Simek 48194846f3SMichal Simek /* Set up the baud rate in gd struct */ 49c54c0a4cSSimon Glass static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, 50c54c0a4cSSimon Glass unsigned long clock, unsigned long baud) 51194846f3SMichal Simek { 52194846f3SMichal Simek /* Calculation results. */ 53194846f3SMichal Simek unsigned int calc_bauderror, bdiv, bgen; 54194846f3SMichal Simek unsigned long calc_baud = 0; 55194846f3SMichal Simek 5604bc5c93SMichal Simek /* Covering case where input clock is so slow */ 57c54c0a4cSSimon Glass if (clock < 1000000 && baud > 4800) 58c54c0a4cSSimon Glass baud = 4800; 5904bc5c93SMichal Simek 60194846f3SMichal Simek /* master clock 61194846f3SMichal Simek * Baud rate = ------------------ 62194846f3SMichal Simek * bgen * (bdiv + 1) 63194846f3SMichal Simek * 64194846f3SMichal Simek * Find acceptable values for baud generation. 65194846f3SMichal Simek */ 66194846f3SMichal Simek for (bdiv = 4; bdiv < 255; bdiv++) { 67194846f3SMichal Simek bgen = clock / (baud * (bdiv + 1)); 68194846f3SMichal Simek if (bgen < 2 || bgen > 65535) 69194846f3SMichal Simek continue; 70194846f3SMichal Simek 71194846f3SMichal Simek calc_baud = clock / (bgen * (bdiv + 1)); 72194846f3SMichal Simek 73194846f3SMichal Simek /* 74194846f3SMichal Simek * Use first calculated baudrate with 75194846f3SMichal Simek * an acceptable (<3%) error 76194846f3SMichal Simek */ 77194846f3SMichal Simek if (baud > calc_baud) 78194846f3SMichal Simek calc_bauderror = baud - calc_baud; 79194846f3SMichal Simek else 80194846f3SMichal Simek calc_bauderror = calc_baud - baud; 81194846f3SMichal Simek if (((calc_bauderror * 100) / baud) < 3) 82194846f3SMichal Simek break; 83194846f3SMichal Simek } 84194846f3SMichal Simek 85194846f3SMichal Simek writel(bdiv, ®s->baud_rate_divider); 86194846f3SMichal Simek writel(bgen, ®s->baud_rate_gen); 87194846f3SMichal Simek } 88194846f3SMichal Simek 89c54c0a4cSSimon Glass /* Initialize the UART, with...some settings. */ 90c54c0a4cSSimon Glass static void _uart_zynq_serial_init(struct uart_zynq *regs) 91c54c0a4cSSimon Glass { 92c54c0a4cSSimon Glass /* RX/TX enabled & reset */ 93c54c0a4cSSimon Glass writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 94c54c0a4cSSimon Glass ZYNQ_UART_CR_RXRST, ®s->control); 95c54c0a4cSSimon Glass writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 96c54c0a4cSSimon Glass } 97c54c0a4cSSimon Glass 98c54c0a4cSSimon Glass static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) 99c54c0a4cSSimon Glass { 1006cd0f2a6SMichal Simek if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) 101c54c0a4cSSimon Glass return -EAGAIN; 102c54c0a4cSSimon Glass 103c54c0a4cSSimon Glass writel(c, ®s->tx_rx_fifo); 104c54c0a4cSSimon Glass 105c54c0a4cSSimon Glass return 0; 106c54c0a4cSSimon Glass } 107c54c0a4cSSimon Glass 10842800ffaSSimon Glass int zynq_serial_setbrg(struct udevice *dev, int baudrate) 109194846f3SMichal Simek { 11042800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 11159da82efSMichal Simek unsigned long clock; 112194846f3SMichal Simek 11359da82efSMichal Simek int ret; 11459da82efSMichal Simek struct clk clk; 11559da82efSMichal Simek 11659da82efSMichal Simek ret = clk_get_by_index(dev, 0, &clk); 11759da82efSMichal Simek if (ret < 0) { 11859da82efSMichal Simek dev_err(dev, "failed to get clock\n"); 11959da82efSMichal Simek return ret; 12059da82efSMichal Simek } 12159da82efSMichal Simek 12259da82efSMichal Simek clock = clk_get_rate(&clk); 12359da82efSMichal Simek if (IS_ERR_VALUE(clock)) { 12459da82efSMichal Simek dev_err(dev, "failed to get rate\n"); 12559da82efSMichal Simek return clock; 12659da82efSMichal Simek } 12759da82efSMichal Simek debug("%s: CLK %ld\n", __func__, clock); 12859da82efSMichal Simek 12959da82efSMichal Simek ret = clk_enable(&clk); 13059da82efSMichal Simek if (ret && ret != -ENOSYS) { 13159da82efSMichal Simek dev_err(dev, "failed to enable clock\n"); 13259da82efSMichal Simek return ret; 13359da82efSMichal Simek } 134*781745bdSStefan Herbrechtsmeier 13542800ffaSSimon Glass _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); 136194846f3SMichal Simek 13742800ffaSSimon Glass return 0; 138194846f3SMichal Simek } 139194846f3SMichal Simek 14042800ffaSSimon Glass static int zynq_serial_probe(struct udevice *dev) 141194846f3SMichal Simek { 14242800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 14342800ffaSSimon Glass 14442800ffaSSimon Glass _uart_zynq_serial_init(priv->regs); 14542800ffaSSimon Glass 14642800ffaSSimon Glass return 0; 147194846f3SMichal Simek } 148194846f3SMichal Simek 14942800ffaSSimon Glass static int zynq_serial_getc(struct udevice *dev) 150194846f3SMichal Simek { 15142800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 15242800ffaSSimon Glass struct uart_zynq *regs = priv->regs; 153194846f3SMichal Simek 15442800ffaSSimon Glass if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) 15542800ffaSSimon Glass return -EAGAIN; 156194846f3SMichal Simek 157194846f3SMichal Simek return readl(®s->tx_rx_fifo); 158194846f3SMichal Simek } 159194846f3SMichal Simek 16042800ffaSSimon Glass static int zynq_serial_putc(struct udevice *dev, const char ch) 161c9416b92SMichal Simek { 16242800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 163c9416b92SMichal Simek 16442800ffaSSimon Glass return _uart_zynq_serial_putc(priv->regs, ch); 165c9416b92SMichal Simek } 16651d8102fSTom Rini 16742800ffaSSimon Glass static int zynq_serial_pending(struct udevice *dev, bool input) 16851d8102fSTom Rini { 16942800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 17042800ffaSSimon Glass struct uart_zynq *regs = priv->regs; 17142800ffaSSimon Glass 17242800ffaSSimon Glass if (input) 17342800ffaSSimon Glass return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); 17442800ffaSSimon Glass else 17542800ffaSSimon Glass return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); 17651d8102fSTom Rini } 177c54c0a4cSSimon Glass 17842800ffaSSimon Glass static int zynq_serial_ofdata_to_platdata(struct udevice *dev) 17942800ffaSSimon Glass { 18042800ffaSSimon Glass struct zynq_uart_priv *priv = dev_get_priv(dev); 18142800ffaSSimon Glass 182842efb3aSMichal Simek priv->regs = (struct uart_zynq *)dev_get_addr(dev); 18342800ffaSSimon Glass 18442800ffaSSimon Glass return 0; 18542800ffaSSimon Glass } 18642800ffaSSimon Glass 18742800ffaSSimon Glass static const struct dm_serial_ops zynq_serial_ops = { 18842800ffaSSimon Glass .putc = zynq_serial_putc, 18942800ffaSSimon Glass .pending = zynq_serial_pending, 19042800ffaSSimon Glass .getc = zynq_serial_getc, 19142800ffaSSimon Glass .setbrg = zynq_serial_setbrg, 19242800ffaSSimon Glass }; 19342800ffaSSimon Glass 19442800ffaSSimon Glass static const struct udevice_id zynq_serial_ids[] = { 19542800ffaSSimon Glass { .compatible = "xlnx,xuartps" }, 19642800ffaSSimon Glass { .compatible = "cdns,uart-r1p8" }, 197a2533183SMichal Simek { .compatible = "cdns,uart-r1p12" }, 19842800ffaSSimon Glass { } 19942800ffaSSimon Glass }; 20042800ffaSSimon Glass 2016bf87dacSMichal Simek U_BOOT_DRIVER(serial_zynq) = { 20242800ffaSSimon Glass .name = "serial_zynq", 20342800ffaSSimon Glass .id = UCLASS_SERIAL, 20442800ffaSSimon Glass .of_match = zynq_serial_ids, 20542800ffaSSimon Glass .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, 20642800ffaSSimon Glass .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), 20742800ffaSSimon Glass .probe = zynq_serial_probe, 20842800ffaSSimon Glass .ops = &zynq_serial_ops, 20942800ffaSSimon Glass .flags = DM_FLAG_PRE_RELOC, 21042800ffaSSimon Glass }; 21142800ffaSSimon Glass 212c54c0a4cSSimon Glass #ifdef CONFIG_DEBUG_UART_ZYNQ 21380dc9997SMichal Simek static inline void _debug_uart_init(void) 214c54c0a4cSSimon Glass { 215c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 216c54c0a4cSSimon Glass 217c54c0a4cSSimon Glass _uart_zynq_serial_init(regs); 218c54c0a4cSSimon Glass _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, 219c54c0a4cSSimon Glass CONFIG_BAUDRATE); 220c54c0a4cSSimon Glass } 221c54c0a4cSSimon Glass 222c54c0a4cSSimon Glass static inline void _debug_uart_putc(int ch) 223c54c0a4cSSimon Glass { 224c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; 225c54c0a4cSSimon Glass 226c54c0a4cSSimon Glass while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) 227c54c0a4cSSimon Glass WATCHDOG_RESET(); 228c54c0a4cSSimon Glass } 229c54c0a4cSSimon Glass 230c54c0a4cSSimon Glass DEBUG_UART_FUNCS 231c54c0a4cSSimon Glass 232c54c0a4cSSimon Glass #endif 233