1194846f3SMichal Simek /* 2194846f3SMichal Simek * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 3194846f3SMichal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. 4194846f3SMichal Simek * 5194846f3SMichal Simek * See file CREDITS for list of people who contributed to this 6194846f3SMichal Simek * project. 7194846f3SMichal Simek * 8194846f3SMichal Simek * This program is free software; you can redistribute it and/or 9194846f3SMichal Simek * modify it under the terms of the GNU General Public License as 10194846f3SMichal Simek * published by the Free Software Foundation; either version 2 of 11194846f3SMichal Simek * the License, or (at your option) any later version. 12194846f3SMichal Simek * 13194846f3SMichal Simek * This program is distributed in the hope that it will be useful, 14194846f3SMichal Simek * but WITHOUT ANY WARRANTY; without even the implied warranty of 15194846f3SMichal Simek * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16194846f3SMichal Simek * GNU General Public License for more details. 17194846f3SMichal Simek * 18194846f3SMichal Simek * You should have received a copy of the GNU General Public License 19194846f3SMichal Simek * along with this program; if not, write to the Free Software 20194846f3SMichal Simek * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21194846f3SMichal Simek * MA 02111-1307 USA 22194846f3SMichal Simek */ 23194846f3SMichal Simek 24194846f3SMichal Simek #include <common.h> 25194846f3SMichal Simek #include <watchdog.h> 26194846f3SMichal Simek #include <asm/io.h> 27194846f3SMichal Simek #include <linux/compiler.h> 28194846f3SMichal Simek #include <serial.h> 29194846f3SMichal Simek 30194846f3SMichal Simek #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 31194846f3SMichal Simek #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 32194846f3SMichal Simek 33194846f3SMichal Simek #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ 34194846f3SMichal Simek #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ 35194846f3SMichal Simek #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ 36194846f3SMichal Simek #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ 37194846f3SMichal Simek 38194846f3SMichal Simek #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 39194846f3SMichal Simek 40194846f3SMichal Simek /* Some clock/baud constants */ 41194846f3SMichal Simek #define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ 42194846f3SMichal Simek #define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ 43194846f3SMichal Simek 44194846f3SMichal Simek struct uart_zynq { 45194846f3SMichal Simek u32 control; /* Control Register [8:0] */ 46194846f3SMichal Simek u32 mode; /* Mode Register [10:0] */ 47194846f3SMichal Simek u32 reserved1[4]; 48194846f3SMichal Simek u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ 49194846f3SMichal Simek u32 reserved2[4]; 50194846f3SMichal Simek u32 channel_sts; /* Channel Status [11:0] */ 51194846f3SMichal Simek u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ 52194846f3SMichal Simek u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ 53194846f3SMichal Simek }; 54194846f3SMichal Simek 55194846f3SMichal Simek static struct uart_zynq *uart_zynq_ports[2] = { 56194846f3SMichal Simek #ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 57194846f3SMichal Simek [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, 58194846f3SMichal Simek #endif 59194846f3SMichal Simek #ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 60194846f3SMichal Simek [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, 61194846f3SMichal Simek #endif 62194846f3SMichal Simek }; 63194846f3SMichal Simek 64194846f3SMichal Simek struct uart_zynq_params { 65194846f3SMichal Simek u32 baudrate; 66194846f3SMichal Simek u32 clock; 67194846f3SMichal Simek }; 68194846f3SMichal Simek 69194846f3SMichal Simek static struct uart_zynq_params uart_zynq_ports_param[2] = { 70194846f3SMichal Simek #if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) 71194846f3SMichal Simek [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, 72194846f3SMichal Simek [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, 73194846f3SMichal Simek #endif 74194846f3SMichal Simek #if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) 75194846f3SMichal Simek [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, 76194846f3SMichal Simek [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, 77194846f3SMichal Simek #endif 78194846f3SMichal Simek }; 79194846f3SMichal Simek 80194846f3SMichal Simek /* Set up the baud rate in gd struct */ 81194846f3SMichal Simek static void uart_zynq_serial_setbrg(const int port) 82194846f3SMichal Simek { 83194846f3SMichal Simek /* Calculation results. */ 84194846f3SMichal Simek unsigned int calc_bauderror, bdiv, bgen; 85194846f3SMichal Simek unsigned long calc_baud = 0; 86194846f3SMichal Simek unsigned long baud = uart_zynq_ports_param[port].baudrate; 87194846f3SMichal Simek unsigned long clock = uart_zynq_ports_param[port].clock; 88194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 89194846f3SMichal Simek 90194846f3SMichal Simek /* master clock 91194846f3SMichal Simek * Baud rate = ------------------ 92194846f3SMichal Simek * bgen * (bdiv + 1) 93194846f3SMichal Simek * 94194846f3SMichal Simek * Find acceptable values for baud generation. 95194846f3SMichal Simek */ 96194846f3SMichal Simek for (bdiv = 4; bdiv < 255; bdiv++) { 97194846f3SMichal Simek bgen = clock / (baud * (bdiv + 1)); 98194846f3SMichal Simek if (bgen < 2 || bgen > 65535) 99194846f3SMichal Simek continue; 100194846f3SMichal Simek 101194846f3SMichal Simek calc_baud = clock / (bgen * (bdiv + 1)); 102194846f3SMichal Simek 103194846f3SMichal Simek /* 104194846f3SMichal Simek * Use first calculated baudrate with 105194846f3SMichal Simek * an acceptable (<3%) error 106194846f3SMichal Simek */ 107194846f3SMichal Simek if (baud > calc_baud) 108194846f3SMichal Simek calc_bauderror = baud - calc_baud; 109194846f3SMichal Simek else 110194846f3SMichal Simek calc_bauderror = calc_baud - baud; 111194846f3SMichal Simek if (((calc_bauderror * 100) / baud) < 3) 112194846f3SMichal Simek break; 113194846f3SMichal Simek } 114194846f3SMichal Simek 115194846f3SMichal Simek writel(bdiv, ®s->baud_rate_divider); 116194846f3SMichal Simek writel(bgen, ®s->baud_rate_gen); 117194846f3SMichal Simek } 118194846f3SMichal Simek 119194846f3SMichal Simek /* Initialize the UART, with...some settings. */ 120194846f3SMichal Simek static int uart_zynq_serial_init(const int port) 121194846f3SMichal Simek { 122194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 123194846f3SMichal Simek 124194846f3SMichal Simek if (!regs) 125194846f3SMichal Simek return -1; 126194846f3SMichal Simek 127194846f3SMichal Simek /* RX/TX enabled & reset */ 128194846f3SMichal Simek writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ 129194846f3SMichal Simek ZYNQ_UART_CR_RXRST, ®s->control); 130194846f3SMichal Simek writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ 131194846f3SMichal Simek uart_zynq_serial_setbrg(port); 132194846f3SMichal Simek 133194846f3SMichal Simek return 0; 134194846f3SMichal Simek } 135194846f3SMichal Simek 136194846f3SMichal Simek static void uart_zynq_serial_putc(const char c, const int port) 137194846f3SMichal Simek { 138194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 139194846f3SMichal Simek 140194846f3SMichal Simek while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) 141194846f3SMichal Simek WATCHDOG_RESET(); 142194846f3SMichal Simek 143194846f3SMichal Simek if (c == '\n') { 144194846f3SMichal Simek writel('\r', ®s->tx_rx_fifo); 145194846f3SMichal Simek while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) 146194846f3SMichal Simek WATCHDOG_RESET(); 147194846f3SMichal Simek } 148194846f3SMichal Simek writel(c, ®s->tx_rx_fifo); 149194846f3SMichal Simek } 150194846f3SMichal Simek 151194846f3SMichal Simek static void uart_zynq_serial_puts(const char *s, const int port) 152194846f3SMichal Simek { 153194846f3SMichal Simek while (*s) 154194846f3SMichal Simek uart_zynq_serial_putc(*s++, port); 155194846f3SMichal Simek } 156194846f3SMichal Simek 157194846f3SMichal Simek static int uart_zynq_serial_tstc(const int port) 158194846f3SMichal Simek { 159194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 160194846f3SMichal Simek 161194846f3SMichal Simek return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; 162194846f3SMichal Simek } 163194846f3SMichal Simek 164194846f3SMichal Simek static int uart_zynq_serial_getc(const int port) 165194846f3SMichal Simek { 166194846f3SMichal Simek struct uart_zynq *regs = uart_zynq_ports[port]; 167194846f3SMichal Simek 168194846f3SMichal Simek while (!uart_zynq_serial_tstc(port)) 169194846f3SMichal Simek WATCHDOG_RESET(); 170194846f3SMichal Simek return readl(®s->tx_rx_fifo); 171194846f3SMichal Simek } 172194846f3SMichal Simek 173194846f3SMichal Simek #if !defined(CONFIG_SERIAL_MULTI) 174194846f3SMichal Simek int serial_init(void) 175194846f3SMichal Simek { 176194846f3SMichal Simek return uart_zynq_serial_init(0); 177194846f3SMichal Simek } 178194846f3SMichal Simek 179194846f3SMichal Simek void serial_setbrg(void) 180194846f3SMichal Simek { 181194846f3SMichal Simek uart_zynq_serial_setbrg(0); 182194846f3SMichal Simek } 183194846f3SMichal Simek 184194846f3SMichal Simek void serial_putc(const char c) 185194846f3SMichal Simek { 186194846f3SMichal Simek uart_zynq_serial_putc(c, 0); 187194846f3SMichal Simek } 188194846f3SMichal Simek 189194846f3SMichal Simek void serial_puts(const char *s) 190194846f3SMichal Simek { 191194846f3SMichal Simek uart_zynq_serial_puts(s, 0); 192194846f3SMichal Simek } 193194846f3SMichal Simek 194194846f3SMichal Simek int serial_getc(void) 195194846f3SMichal Simek { 196194846f3SMichal Simek return uart_zynq_serial_getc(0); 197194846f3SMichal Simek } 198194846f3SMichal Simek 199194846f3SMichal Simek int serial_tstc(void) 200194846f3SMichal Simek { 201194846f3SMichal Simek return uart_zynq_serial_tstc(0); 202194846f3SMichal Simek } 203194846f3SMichal Simek #else 204194846f3SMichal Simek /* Multi serial device functions */ 205194846f3SMichal Simek #define DECLARE_PSSERIAL_FUNCTIONS(port) \ 206194846f3SMichal Simek int uart_zynq##port##_init(void) \ 207194846f3SMichal Simek { return uart_zynq_serial_init(port); } \ 208194846f3SMichal Simek void uart_zynq##port##_setbrg(void) \ 209194846f3SMichal Simek { return uart_zynq_serial_setbrg(port); } \ 210194846f3SMichal Simek int uart_zynq##port##_getc(void) \ 211194846f3SMichal Simek { return uart_zynq_serial_getc(port); } \ 212194846f3SMichal Simek int uart_zynq##port##_tstc(void) \ 213194846f3SMichal Simek { return uart_zynq_serial_tstc(port); } \ 214194846f3SMichal Simek void uart_zynq##port##_putc(const char c) \ 215194846f3SMichal Simek { uart_zynq_serial_putc(c, port); } \ 216194846f3SMichal Simek void uart_zynq##port##_puts(const char *s) \ 217194846f3SMichal Simek { uart_zynq_serial_puts(s, port); } 218194846f3SMichal Simek 219194846f3SMichal Simek /* Serial device descriptor */ 220194846f3SMichal Simek #define INIT_PSSERIAL_STRUCTURE(port, __name) { \ 221194846f3SMichal Simek .name = __name, \ 22289143fb3SMarek Vasut .start = uart_zynq##port##_init, \ 22389143fb3SMarek Vasut .stop = NULL, \ 224194846f3SMichal Simek .setbrg = uart_zynq##port##_setbrg, \ 225194846f3SMichal Simek .getc = uart_zynq##port##_getc, \ 226194846f3SMichal Simek .tstc = uart_zynq##port##_tstc, \ 227194846f3SMichal Simek .putc = uart_zynq##port##_putc, \ 228194846f3SMichal Simek .puts = uart_zynq##port##_puts, \ 229194846f3SMichal Simek } 230194846f3SMichal Simek 231194846f3SMichal Simek DECLARE_PSSERIAL_FUNCTIONS(0); 232194846f3SMichal Simek struct serial_device uart_zynq_serial0_device = 233194846f3SMichal Simek INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); 234194846f3SMichal Simek DECLARE_PSSERIAL_FUNCTIONS(1); 235194846f3SMichal Simek struct serial_device uart_zynq_serial1_device = 236194846f3SMichal Simek INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); 237194846f3SMichal Simek 238194846f3SMichal Simek __weak struct serial_device *default_serial_console(void) 239194846f3SMichal Simek { 240194846f3SMichal Simek if (uart_zynq_ports[0]) 241194846f3SMichal Simek return &uart_zynq_serial0_device; 242194846f3SMichal Simek if (uart_zynq_ports[1]) 243194846f3SMichal Simek return &uart_zynq_serial1_device; 244194846f3SMichal Simek 245194846f3SMichal Simek return NULL; 246194846f3SMichal Simek } 247194846f3SMichal Simek #endif 248*51d8102fSTom Rini 249*51d8102fSTom Rini void zynq_serial_initalize(void) 250*51d8102fSTom Rini { 251*51d8102fSTom Rini #ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 252*51d8102fSTom Rini serial_register(&uart_zynq_serial0_device); 253*51d8102fSTom Rini #endif 254*51d8102fSTom Rini #ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 255*51d8102fSTom Rini serial_register(&uart_zynq_serial1_device); 256*51d8102fSTom Rini #endif 257*51d8102fSTom Rini } 258