1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012-2015 Panasonic Corporation 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <linux/bug.h> 11 #include <linux/io.h> 12 #include <linux/serial_reg.h> 13 #include <linux/sizes.h> 14 #include <linux/errno.h> 15 #include <serial.h> 16 #include <fdtdec.h> 17 18 /* 19 * Note: Register map is slightly different from that of 16550. 20 */ 21 struct uniphier_serial { 22 u32 rx; /* In: Receive buffer */ 23 #define tx rx /* Out: Transmit buffer */ 24 u32 ier; /* Interrupt Enable Register */ 25 u32 iir; /* In: Interrupt ID Register */ 26 u32 char_fcr; /* Charactor / FIFO Control Register */ 27 u32 lcr_mcr; /* Line/Modem Control Register */ 28 #define LCR_SHIFT 8 29 #define LCR_MASK (0xff << (LCR_SHIFT)) 30 u32 lsr; /* In: Line Status Register */ 31 u32 msr; /* In: Modem Status Register */ 32 u32 __rsv0; 33 u32 __rsv1; 34 u32 dlr; /* Divisor Latch Register */ 35 }; 36 37 struct uniphier_serial_priv { 38 struct uniphier_serial __iomem *membase; 39 unsigned int uartclk; 40 }; 41 42 #define uniphier_serial_port(dev) \ 43 ((struct uniphier_serial_priv *)dev_get_priv(dev))->membase 44 45 static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) 46 { 47 struct uniphier_serial_priv *priv = dev_get_priv(dev); 48 struct uniphier_serial __iomem *port = uniphier_serial_port(dev); 49 const unsigned int mode_x_div = 16; 50 unsigned int divisor; 51 52 divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate); 53 54 writel(divisor, &port->dlr); 55 56 return 0; 57 } 58 59 static int uniphier_serial_getc(struct udevice *dev) 60 { 61 struct uniphier_serial __iomem *port = uniphier_serial_port(dev); 62 63 if (!(readl(&port->lsr) & UART_LSR_DR)) 64 return -EAGAIN; 65 66 return readl(&port->rx); 67 } 68 69 static int uniphier_serial_putc(struct udevice *dev, const char c) 70 { 71 struct uniphier_serial __iomem *port = uniphier_serial_port(dev); 72 73 if (!(readl(&port->lsr) & UART_LSR_THRE)) 74 return -EAGAIN; 75 76 writel(c, &port->tx); 77 78 return 0; 79 } 80 81 static int uniphier_serial_pending(struct udevice *dev, bool input) 82 { 83 struct uniphier_serial __iomem *port = uniphier_serial_port(dev); 84 85 if (input) 86 return readl(&port->lsr) & UART_LSR_DR; 87 else 88 return !(readl(&port->lsr) & UART_LSR_THRE); 89 } 90 91 /* 92 * SPL does not have enough memory footprint for the clock driver. 93 * Hardcode clock frequency for each SoC. 94 */ 95 struct uniphier_serial_clk_data { 96 const char *compatible; 97 unsigned int clk_rate; 98 }; 99 100 static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = { 101 { .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 }, 102 { .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 }, 103 { .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 }, 104 { .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 }, 105 { .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 }, 106 { .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 }, 107 { .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 }, 108 { .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 }, 109 { .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 }, 110 { /* sentinel */ }, 111 }; 112 113 static int uniphier_serial_probe(struct udevice *dev) 114 { 115 struct uniphier_serial_priv *priv = dev_get_priv(dev); 116 struct uniphier_serial __iomem *port; 117 const struct uniphier_serial_clk_data *clk_data; 118 ofnode root_node; 119 fdt_addr_t base; 120 u32 tmp; 121 122 base = devfdt_get_addr(dev); 123 if (base == FDT_ADDR_T_NONE) 124 return -EINVAL; 125 126 port = devm_ioremap(dev, base, SZ_64); 127 if (!port) 128 return -ENOMEM; 129 130 priv->membase = port; 131 132 root_node = ofnode_path("/"); 133 clk_data = uniphier_serial_clk_data; 134 while (clk_data->compatible) { 135 if (ofnode_device_is_compatible(root_node, 136 clk_data->compatible)) 137 break; 138 clk_data++; 139 } 140 141 if (WARN_ON(!clk_data->compatible)) 142 return -ENOTSUPP; 143 144 priv->uartclk = clk_data->clk_rate; 145 146 tmp = readl(&port->lcr_mcr); 147 tmp &= ~LCR_MASK; 148 tmp |= UART_LCR_WLEN8 << LCR_SHIFT; 149 writel(tmp, &port->lcr_mcr); 150 151 return 0; 152 } 153 154 static const struct udevice_id uniphier_uart_of_match[] = { 155 { .compatible = "socionext,uniphier-uart" }, 156 { /* sentinel */ } 157 }; 158 159 static const struct dm_serial_ops uniphier_serial_ops = { 160 .setbrg = uniphier_serial_setbrg, 161 .getc = uniphier_serial_getc, 162 .putc = uniphier_serial_putc, 163 .pending = uniphier_serial_pending, 164 }; 165 166 U_BOOT_DRIVER(uniphier_serial) = { 167 .name = "uniphier-uart", 168 .id = UCLASS_SERIAL, 169 .of_match = uniphier_uart_of_match, 170 .probe = uniphier_serial_probe, 171 .priv_auto_alloc_size = sizeof(struct uniphier_serial_priv), 172 .ops = &uniphier_serial_ops, 173 }; 174