1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5  */
6 
7 #ifndef _SERIAL_STM32_
8 #define _SERIAL_STM32_
9 
10 #define CR1_OFFSET(x)	(x ? 0x0c : 0x00)
11 #define CR3_OFFSET(x)	(x ? 0x14 : 0x08)
12 #define BRR_OFFSET(x)	(x ? 0x08 : 0x0c)
13 #define ISR_OFFSET(x)	(x ? 0x00 : 0x1c)
14 
15 #define ICR_OFFSET	0x20
16 
17 /*
18  * STM32F4 has one Data Register (DR) for received or transmitted
19  * data, so map Receive Data Register (RDR) and Transmit Data
20  * Register (TDR) at the same offset
21  */
22 #define RDR_OFFSET(x)	(x ? 0x04 : 0x24)
23 #define TDR_OFFSET(x)	(x ? 0x04 : 0x28)
24 
25 struct stm32_uart_info {
26 	u8 uart_enable_bit;	/* UART_CR1_UE */
27 	bool stm32f4;		/* true for STM32F4, false otherwise */
28 	bool has_fifo;
29 };
30 
31 struct stm32_uart_info stm32f4_info = {
32 	.stm32f4 = true,
33 	.uart_enable_bit = 13,
34 	.has_fifo = false,
35 };
36 
37 struct stm32_uart_info stm32f7_info = {
38 	.uart_enable_bit = 0,
39 	.stm32f4 = false,
40 	.has_fifo = false,
41 };
42 
43 struct stm32_uart_info stm32h7_info = {
44 	.uart_enable_bit = 0,
45 	.stm32f4 = false,
46 	.has_fifo = true,
47 };
48 
49 /* Information about a serial port */
50 struct stm32x7_serial_platdata {
51 	fdt_addr_t base;  /* address of registers in physical memory */
52 	struct stm32_uart_info *uart_info;
53 	unsigned long int clock_rate;
54 };
55 
56 #define USART_CR1_FIFOEN		BIT(29)
57 #define USART_CR1_M1			BIT(28)
58 #define USART_CR1_OVER8			BIT(15)
59 #define USART_CR1_M0			BIT(12)
60 #define USART_CR1_PCE			BIT(10)
61 #define USART_CR1_PS			BIT(9)
62 #define USART_CR1_TE			BIT(3)
63 #define USART_CR1_RE			BIT(2)
64 
65 #define USART_CR3_OVRDIS		BIT(12)
66 
67 #define USART_ISR_TXE			BIT(7)
68 #define USART_ISR_RXNE			BIT(5)
69 #define USART_ISR_ORE			BIT(3)
70 #define USART_ISR_PE			BIT(0)
71 
72 #define USART_BRR_F_MASK		GENMASK(7, 0)
73 #define USART_BRR_M_SHIFT		4
74 #define USART_BRR_M_MASK		GENMASK(15, 4)
75 
76 #define USART_ICR_ORECF			BIT(3)
77 #define USART_ICR_PCECF			BIT(0)
78 
79 #endif
80