1 /* 2 * Copy and modify from linux/drivers/serial/sh-sci.h 3 */ 4 5 struct uart_port { 6 unsigned long iobase; /* in/out[bwl] */ 7 unsigned char *membase; /* read/write[bwl] */ 8 unsigned long mapbase; /* for ioremap */ 9 unsigned int type; /* port type */ 10 }; 11 12 #define PORT_SCI 52 13 #define PORT_SCIF 53 14 #define PORT_SCIFA 83 15 #define PORT_SCIFB 93 16 17 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 18 #include <asm/regs306x.h> 19 #endif 20 #if defined(CONFIG_H8S2678) 21 #include <asm/regs267x.h> 22 #endif 23 24 #if defined(CONFIG_CPU_SH7706) || \ 25 defined(CONFIG_CPU_SH7707) || \ 26 defined(CONFIG_CPU_SH7708) || \ 27 defined(CONFIG_CPU_SH7709) 28 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 29 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 30 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 31 #elif defined(CONFIG_CPU_SH7705) 32 # define SCIF0 0xA4400000 33 # define SCIF2 0xA4410000 34 # define SCSMR_Ir 0xA44A0000 35 # define IRDA_SCIF SCIF0 36 # define SCPCR 0xA4000116 37 # define SCPDR 0xA4000136 38 39 /* Set the clock source, 40 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 41 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 42 */ 43 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 44 #elif defined(CONFIG_CPU_SH7720) || \ 45 defined(CONFIG_CPU_SH7721) || \ 46 defined(CONFIG_ARCH_SH7367) || \ 47 defined(CONFIG_ARCH_SH7377) || \ 48 defined(CONFIG_ARCH_SH7372) || \ 49 defined(CONFIG_SH73A0) || \ 50 defined(CONFIG_R8A7740) 51 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 52 # define PORT_PTCR 0xA405011EUL 53 # define PORT_PVCR 0xA4050122UL 54 # define SCIF_ORER 0x0200 /* overrun error bit */ 55 #elif defined(CONFIG_SH_RTS7751R2D) 56 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 57 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 58 # define SCIF_ORER 0x0001 /* overrun error bit */ 59 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 60 #elif defined(CONFIG_CPU_SH7750) || \ 61 defined(CONFIG_CPU_SH7750R) || \ 62 defined(CONFIG_CPU_SH7750S) || \ 63 defined(CONFIG_CPU_SH7091) || \ 64 defined(CONFIG_CPU_SH7751) || \ 65 defined(CONFIG_CPU_SH7751R) 66 # define SCSPTR1 0xffe0001c /* 8 bit SCI */ 67 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 68 # define SCIF_ORER 0x0001 /* overrun error bit */ 69 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 70 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 71 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 72 #elif defined(CONFIG_CPU_SH7760) 73 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 74 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 75 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 76 # define SCIF_ORER 0x0001 /* overrun error bit */ 77 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 78 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 79 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 80 # define SCIF_ORER 0x0001 /* overrun error bit */ 81 # define PACR 0xa4050100 82 # define PBCR 0xa4050102 83 # define SCSCR_INIT(port) 0x3B 84 #elif defined(CONFIG_CPU_SH7343) 85 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 86 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 87 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 88 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 89 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 90 #elif defined(CONFIG_CPU_SH7722) 91 # define PADR 0xA4050120 92 # undef PSDR 93 # define PSDR 0xA405013e 94 # define PWDR 0xA4050166 95 # define PSCR 0xA405011E 96 # define SCIF_ORER 0x0001 /* overrun error bit */ 97 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 98 #elif defined(CONFIG_CPU_SH7366) 99 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 100 # define SCSPTR0 SCPDR0 101 # define SCIF_ORER 0x0001 /* overrun error bit */ 102 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 103 #elif defined(CONFIG_CPU_SH7723) 104 # define SCSPTR0 0xa4050160 105 # define SCSPTR1 0xa405013e 106 # define SCSPTR2 0xa4050160 107 # define SCSPTR3 0xa405013e 108 # define SCSPTR4 0xa4050128 109 # define SCSPTR5 0xa4050128 110 # define SCIF_ORER 0x0001 /* overrun error bit */ 111 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 112 #elif defined(CONFIG_CPU_SH7724) 113 # define SCIF_ORER 0x0001 /* overrun error bit */ 114 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 115 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 116 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 117 #elif defined(CONFIG_CPU_SH7734) 118 # define SCSPTR0 0xFFE40020 119 # define SCSPTR1 0xFFE41020 120 # define SCSPTR2 0xFFE42020 121 # define SCSPTR3 0xFFE43020 122 # define SCSPTR4 0xFFE44020 123 # define SCSPTR5 0xFFE45020 124 # define SCIF_ORER 0x0001 /* overrun error bit */ 125 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 126 #elif defined(CONFIG_CPU_SH4_202) 127 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 128 # define SCIF_ORER 0x0001 /* overrun error bit */ 129 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 130 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) 131 # define SCIF_BASE_ADDR 0x01030000 132 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) 133 # define SCIF_PTR2_OFFS 0x0000020 134 # define SCIF_LSR2_OFFS 0x0000024 135 # define SCSPTR\ 136 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 137 # define SCLSR2\ 138 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 139 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 140 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 141 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 142 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 143 #elif defined(CONFIG_H8S2678) 144 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 145 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 146 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 147 # define SCSPTR0 0xfe4b0020 148 # define SCSPTR1 0xfe4b0020 149 # define SCSPTR2 0xfe4b0020 150 # define SCIF_ORER 0x0001 151 # define SCSCR_INIT(port) 0x38 152 # define SCIF_ONLY 153 #elif defined(CONFIG_CPU_SH7763) 154 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 155 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 156 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 157 # define SCIF_ORER 0x0001 /* overrun error bit */ 158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 159 #elif defined(CONFIG_CPU_SH7770) 160 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 161 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 162 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 163 # define SCIF_ORER 0x0001 /* overrun error bit */ 164 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 165 #elif defined(CONFIG_CPU_SH7780) 166 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 167 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 168 # define SCIF_ORER 0x0001 /* Overrun error bit */ 169 170 #if defined(CONFIG_SH_SH2007) 171 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ 172 # define SCSCR_INIT(port) 0x38 173 #else 174 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ 175 # define SCSCR_INIT(port) 0x3a 176 #endif 177 178 #elif defined(CONFIG_CPU_SH7785) || \ 179 defined(CONFIG_CPU_SH7786) 180 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 181 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 182 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 183 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 184 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 185 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 186 # define SCIF_ORER 0x0001 /* Overrun error bit */ 187 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 188 #elif defined(CONFIG_CPU_SH7201) || \ 189 defined(CONFIG_CPU_SH7203) || \ 190 defined(CONFIG_CPU_SH7206) || \ 191 defined(CONFIG_CPU_SH7263) || \ 192 defined(CONFIG_CPU_SH7264) 193 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 194 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 195 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 196 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 197 # if defined(CONFIG_CPU_SH7201) 198 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 199 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 200 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 201 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 202 # endif 203 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 204 #elif defined(CONFIG_CPU_SH7269) 205 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ 206 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ 207 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ 208 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */ 209 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */ 210 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */ 211 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ 212 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ 213 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 214 #elif defined(CONFIG_CPU_SH7619) 215 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 216 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 217 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 218 # define SCIF_ORER 0x0001 /* overrun error bit */ 219 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 220 #elif defined(CONFIG_CPU_SHX3) 221 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 222 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 223 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 224 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 225 # define SCIF_ORER 0x0001 /* Overrun error bit */ 226 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 227 #else 228 # error CPU subtype not defined 229 #endif 230 231 /* SCSCR */ 232 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 233 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 234 #define SCI_CTRL_FLAGS_TE 0x20 /* all */ 235 #define SCI_CTRL_FLAGS_RE 0x10 /* all */ 236 #if defined(CONFIG_CPU_SH7750) || \ 237 defined(CONFIG_CPU_SH7091) || \ 238 defined(CONFIG_CPU_SH7750R) || \ 239 defined(CONFIG_CPU_SH7722) || \ 240 defined(CONFIG_CPU_SH7734) || \ 241 defined(CONFIG_CPU_SH7750S) || \ 242 defined(CONFIG_CPU_SH7751) || \ 243 defined(CONFIG_CPU_SH7751R) || \ 244 defined(CONFIG_CPU_SH7763) || \ 245 defined(CONFIG_CPU_SH7780) || \ 246 defined(CONFIG_CPU_SH7785) || \ 247 defined(CONFIG_CPU_SH7786) || \ 248 defined(CONFIG_CPU_SHX3) 249 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 250 #elif defined(CONFIG_CPU_SH7724) 251 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) 252 #else 253 #define SCI_CTRL_FLAGS_REIE 0 254 #endif 255 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 256 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 257 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 258 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 259 260 /* SCxSR SCI */ 261 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 262 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 263 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 264 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 265 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 266 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 267 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 268 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 269 270 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 271 272 /* SCxSR SCIF */ 273 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 274 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 275 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 276 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 277 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 278 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 279 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 280 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 281 282 #if defined(CONFIG_CPU_SH7705) || \ 283 defined(CONFIG_CPU_SH7720) || \ 284 defined(CONFIG_CPU_SH7721) || \ 285 defined(CONFIG_ARCH_SH7367) || \ 286 defined(CONFIG_ARCH_SH7377) || \ 287 defined(CONFIG_ARCH_SH7372) || \ 288 defined(CONFIG_SH73A0) || \ 289 defined(CONFIG_R8A7740) 290 # define SCIF_ORER 0x0200 291 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 292 # define SCIF_RFDC_MASK 0x007f 293 # define SCIF_TXROOM_MAX 64 294 #elif defined(CONFIG_CPU_SH7763) 295 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 296 # define SCIF_RFDC_MASK 0x007f 297 # define SCIF_TXROOM_MAX 64 298 /* SH7763 SCIF2 support */ 299 # define SCIF2_RFDC_MASK 0x001f 300 # define SCIF2_TXROOM_MAX 16 301 #else 302 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 303 # define SCIF_RFDC_MASK 0x001f 304 # define SCIF_TXROOM_MAX 16 305 #endif 306 307 #ifndef SCIF_ORER 308 #define SCIF_ORER 0x0000 309 #endif 310 311 #define SCxSR_TEND(port)\ 312 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 313 #define SCxSR_ERRORS(port)\ 314 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 315 #define SCxSR_RDxF(port)\ 316 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 317 #define SCxSR_TDxE(port)\ 318 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 319 #define SCxSR_FER(port)\ 320 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 321 #define SCxSR_PER(port)\ 322 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 323 #define SCxSR_BRK(port)\ 324 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 325 #define SCxSR_ORER(port)\ 326 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 327 328 #if defined(CONFIG_CPU_SH7705) || \ 329 defined(CONFIG_CPU_SH7720) || \ 330 defined(CONFIG_CPU_SH7721) || \ 331 defined(CONFIG_ARCH_SH7367) || \ 332 defined(CONFIG_ARCH_SH7377) || \ 333 defined(CONFIG_ARCH_SH7372) || \ 334 defined(CONFIG_SH73A0) || \ 335 defined(CONFIG_R8A7740) 336 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 337 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 338 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 339 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 340 #else 341 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 342 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 343 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 344 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 345 #endif 346 347 /* SCFCR */ 348 #define SCFCR_RFRST 0x0002 349 #define SCFCR_TFRST 0x0004 350 #define SCFCR_TCRST 0x4000 351 #define SCFCR_MCE 0x0008 352 353 #define SCI_MAJOR 204 354 #define SCI_MINOR_START 8 355 356 /* Generic serial flags */ 357 #define SCI_RX_THROTTLE 0x0000001 358 359 #define SCI_MAGIC 0xbabeface 360 361 /* 362 * Events are used to schedule things to happen at timer-interrupt 363 * time, instead of at rs interrupt time. 364 */ 365 #define SCI_EVENT_WRITE_WAKEUP 0 366 367 #define SCI_IN(size, offset)\ 368 if ((size) == 8) {\ 369 return readb(port->membase + (offset));\ 370 } else {\ 371 return readw(port->membase + (offset));\ 372 } 373 #define SCI_OUT(size, offset, value)\ 374 if ((size) == 8) {\ 375 writeb(value, port->membase + (offset));\ 376 } else if ((size) == 16) {\ 377 writew(value, port->membase + (offset));\ 378 } 379 380 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 381 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 382 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 383 SCI_IN(scif_size, scif_offset)\ 384 } else { /* PORT_SCI or PORT_SCIFA */\ 385 SCI_IN(sci_size, sci_offset);\ 386 }\ 387 }\ 388 static inline void sci_##name##_out(struct uart_port *port,\ 389 unsigned int value) {\ 390 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 391 SCI_OUT(scif_size, scif_offset, value)\ 392 } else { /* PORT_SCI or PORT_SCIFA */\ 393 SCI_OUT(sci_size, sci_offset, value);\ 394 }\ 395 } 396 397 #ifdef CONFIG_H8300 398 /* h8300 don't have SCIF */ 399 #define CPU_SCIF_FNS(name) \ 400 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 401 return 0;\ 402 }\ 403 static inline void sci_##name##_out(struct uart_port *port,\ 404 unsigned int value) {\ 405 } 406 #else 407 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 408 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 409 SCI_IN(scif_size, scif_offset);\ 410 }\ 411 static inline void sci_##name##_out(struct uart_port *port,\ 412 unsigned int value) {\ 413 SCI_OUT(scif_size, scif_offset, value);\ 414 } 415 #endif 416 417 #define CPU_SCI_FNS(name, sci_offset, sci_size)\ 418 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 419 SCI_IN(sci_size, sci_offset);\ 420 }\ 421 static inline void sci_##name##_out(struct uart_port *port,\ 422 unsigned int value) {\ 423 SCI_OUT(sci_size, sci_offset, value);\ 424 } 425 426 #if defined(CONFIG_SH3) || \ 427 defined(CONFIG_ARCH_SH7367) || \ 428 defined(CONFIG_ARCH_SH7377) || \ 429 defined(CONFIG_ARCH_SH7372) || \ 430 defined(CONFIG_SH73A0) || \ 431 defined(CONFIG_R8A7740) 432 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 433 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 434 sh4_sci_offset, sh4_sci_size, \ 435 sh3_scif_offset, sh3_scif_size, \ 436 sh4_scif_offset, sh4_scif_size, \ 437 h8_sci_offset, h8_sci_size) \ 438 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 439 sh4_scif_offset, sh4_scif_size) 440 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 441 sh4_scif_offset, sh4_scif_size) \ 442 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 443 #elif defined(CONFIG_CPU_SH7705) || \ 444 defined(CONFIG_CPU_SH7720) || \ 445 defined(CONFIG_CPU_SH7721) || \ 446 defined(CONFIG_ARCH_SH7367) || \ 447 defined(CONFIG_ARCH_SH7377) || \ 448 defined(CONFIG_SH73A0) 449 #define SCIF_FNS(name, scif_offset, scif_size) \ 450 CPU_SCIF_FNS(name, scif_offset, scif_size) 451 #elif defined(CONFIG_ARCH_SH7372) || \ 452 defined(CONFIG_R8A7740) 453 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 454 sh4_scifb_offset, sh4_scifb_size) \ 455 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 456 sh4_scifb_offset, sh4_scifb_size) 457 #define SCIF_FNS(name, scif_offset, scif_size) \ 458 CPU_SCIF_FNS(name, scif_offset, scif_size) 459 #else 460 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 461 sh4_sci_offset, sh4_sci_size, \ 462 sh3_scif_offset, sh3_scif_size,\ 463 sh4_scif_offset, sh4_scif_size, \ 464 h8_sci_offset, h8_sci_size) \ 465 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 466 sh3_scif_offset, sh3_scif_size) 467 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 468 sh4_scif_offset, sh4_scif_size) \ 469 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 470 #endif 471 #elif defined(__H8300H__) || defined(__H8300S__) 472 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 473 sh4_sci_offset, sh4_sci_size, \ 474 sh3_scif_offset, sh3_scif_size,\ 475 sh4_scif_offset, sh4_scif_size, \ 476 h8_sci_offset, h8_sci_size) \ 477 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 478 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 479 sh4_scif_offset, sh4_scif_size) \ 480 CPU_SCIF_FNS(name) 481 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) 482 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 483 sh4_scif_offset, sh4_scif_size) \ 484 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 485 sh4_scif_offset, sh4_scif_size) 486 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 487 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 488 #else 489 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 490 sh4_sci_offset, sh4_sci_size, \ 491 sh3_scif_offset, sh3_scif_size,\ 492 sh4_scif_offset, sh4_scif_size, \ 493 h8_sci_offset, h8_sci_size) \ 494 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 495 sh4_scif_offset, sh4_scif_size) 496 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ 497 sh4_scif_offset, sh4_scif_size) \ 498 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 499 #endif 500 501 #if defined(CONFIG_CPU_SH7705) || \ 502 defined(CONFIG_CPU_SH7720) || \ 503 defined(CONFIG_CPU_SH7721) || \ 504 defined(CONFIG_ARCH_SH7367) || \ 505 defined(CONFIG_ARCH_SH7377) || \ 506 defined(CONFIG_SH73A0) 507 508 SCIF_FNS(SCSMR, 0x00, 16) 509 SCIF_FNS(SCBRR, 0x04, 8) 510 SCIF_FNS(SCSCR, 0x08, 16) 511 SCIF_FNS(SCTDSR, 0x0c, 8) 512 SCIF_FNS(SCFER, 0x10, 16) 513 SCIF_FNS(SCxSR, 0x14, 16) 514 SCIF_FNS(SCFCR, 0x18, 16) 515 SCIF_FNS(SCFDR, 0x1c, 16) 516 SCIF_FNS(SCxTDR, 0x20, 8) 517 SCIF_FNS(SCxRDR, 0x24, 8) 518 SCIF_FNS(SCLSR, 0x00, 0) 519 #elif defined(CONFIG_ARCH_SH7372) || \ 520 defined(CONFIG_R8A7740) 521 SCIF_FNS(SCSMR, 0x00, 16) 522 SCIF_FNS(SCBRR, 0x04, 8) 523 SCIF_FNS(SCSCR, 0x08, 16) 524 SCIF_FNS(SCTDSR, 0x0c, 16) 525 SCIF_FNS(SCFER, 0x10, 16) 526 SCIF_FNS(SCxSR, 0x14, 16) 527 SCIF_FNS(SCFCR, 0x18, 16) 528 SCIF_FNS(SCFDR, 0x1c, 16) 529 SCIF_FNS(SCTFDR, 0x38, 16) 530 SCIF_FNS(SCRFDR, 0x3c, 16) 531 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 532 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 533 SCIF_FNS(SCLSR, 0x00, 0) 534 #elif defined(CONFIG_CPU_SH7723) ||\ 535 defined(CONFIG_CPU_SH7724) 536 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 537 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 538 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 539 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 540 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 541 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 542 SCIx_FNS(SCSPTR, 0, 0, 0, 0) 543 SCIF_FNS(SCTDSR, 0x0c, 8) 544 SCIF_FNS(SCFER, 0x10, 16) 545 SCIF_FNS(SCFCR, 0x18, 16) 546 SCIF_FNS(SCFDR, 0x1c, 16) 547 SCIF_FNS(SCLSR, 0x24, 16) 548 #else 549 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 550 /* name off sz off sz off sz off sz off sz*/ 551 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 552 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 553 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 554 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 555 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 556 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 557 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 558 #if defined(CONFIG_CPU_SH7760) || \ 559 defined(CONFIG_CPU_SH7780) || \ 560 defined(CONFIG_CPU_SH7785) || \ 561 defined(CONFIG_CPU_SH7786) 562 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 563 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 564 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 565 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 566 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 567 #elif defined(CONFIG_CPU_SH7763) 568 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 569 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 570 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) 571 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 572 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 573 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 574 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 575 #else 576 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 577 #if defined(CONFIG_CPU_SH7722) 578 SCIF_FNS(SCSPTR, 0, 0, 0, 0) 579 #else 580 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 581 #endif 582 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 583 #endif 584 #endif 585 #define sci_in(port, reg) sci_##reg##_in(port) 586 #define sci_out(port, reg, value) sci_##reg##_out(port, value) 587 588 /* H8/300 series SCI pins assignment */ 589 #if defined(__H8300H__) || defined(__H8300S__) 590 static const struct __attribute__((packed)) { 591 int port; /* GPIO port no */ 592 unsigned short rx, tx; /* GPIO bit no */ 593 } h8300_sci_pins[] = { 594 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 595 { /* SCI0 */ 596 .port = H8300_GPIO_P9, 597 .rx = H8300_GPIO_B2, 598 .tx = H8300_GPIO_B0, 599 }, 600 { /* SCI1 */ 601 .port = H8300_GPIO_P9, 602 .rx = H8300_GPIO_B3, 603 .tx = H8300_GPIO_B1, 604 }, 605 { /* SCI2 */ 606 .port = H8300_GPIO_PB, 607 .rx = H8300_GPIO_B7, 608 .tx = H8300_GPIO_B6, 609 } 610 #elif defined(CONFIG_H8S2678) 611 { /* SCI0 */ 612 .port = H8300_GPIO_P3, 613 .rx = H8300_GPIO_B2, 614 .tx = H8300_GPIO_B0, 615 }, 616 { /* SCI1 */ 617 .port = H8300_GPIO_P3, 618 .rx = H8300_GPIO_B3, 619 .tx = H8300_GPIO_B1, 620 }, 621 { /* SCI2 */ 622 .port = H8300_GPIO_P5, 623 .rx = H8300_GPIO_B1, 624 .tx = H8300_GPIO_B0, 625 } 626 #endif 627 }; 628 #endif 629 630 #if defined(CONFIG_CPU_SH7706) || \ 631 defined(CONFIG_CPU_SH7707) || \ 632 defined(CONFIG_CPU_SH7708) || \ 633 defined(CONFIG_CPU_SH7709) 634 static inline int sci_rxd_in(struct uart_port *port) 635 { 636 if (port->mapbase == 0xfffffe80) 637 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 638 return 1; 639 } 640 #elif defined(CONFIG_CPU_SH7750) || \ 641 defined(CONFIG_CPU_SH7751) || \ 642 defined(CONFIG_CPU_SH7751R) || \ 643 defined(CONFIG_CPU_SH7750R) || \ 644 defined(CONFIG_CPU_SH7750S) || \ 645 defined(CONFIG_CPU_SH7091) 646 static inline int sci_rxd_in(struct uart_port *port) 647 { 648 if (port->mapbase == 0xffe00000) 649 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 650 return 1; 651 } 652 #elif defined(__H8300H__) || defined(__H8300S__) 653 static inline int sci_rxd_in(struct uart_port *port) 654 { 655 int ch = (port->mapbase - SMR0) >> 3; 656 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 657 } 658 #else /* default case for non-SCI processors */ 659 static inline int sci_rxd_in(struct uart_port *port) 660 { 661 return 1; 662 } 663 #endif 664 665 /* 666 * Values for the BitRate Register (SCBRR) 667 * 668 * The values are actually divisors for a frequency which can 669 * be internal to the SH3 (14.7456MHz) or derived from an external 670 * clock source. This driver assumes the internal clock is used; 671 * to support using an external clock source, config options or 672 * possibly command-line options would need to be added. 673 * 674 * Also, to support speeds below 2400 (why?) the lower 2 bits of 675 * the SCSMR register would also need to be set to non-zero values. 676 * 677 * -- Greg Banks 27Feb2000 678 * 679 * Answer: The SCBRR register is only eight bits, and the value in 680 * it gets larger with lower baud rates. At around 2400 (depending on 681 * the peripherial module clock) you run out of bits. However the 682 * lower two bits of SCSMR allow the module clock to be divided down, 683 * scaling the value which is needed in SCBRR. 684 * 685 * -- Stuart Menefy - 23 May 2000 686 * 687 * I meant, why would anyone bother with bitrates below 2400. 688 * 689 * -- Greg Banks - 7Jul2000 690 * 691 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 692 * tape reader as a console! 693 * 694 * -- Mitch Davis - 15 Jul 2000 695 */ 696 697 #if (defined(CONFIG_CPU_SH7780) || \ 698 defined(CONFIG_CPU_SH7785) || \ 699 defined(CONFIG_CPU_SH7786)) && \ 700 !defined(CONFIG_SH_SH2007) 701 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 702 #elif defined(CONFIG_CPU_SH7705) || \ 703 defined(CONFIG_CPU_SH7720) || \ 704 defined(CONFIG_CPU_SH7721) || \ 705 defined(CONFIG_ARCH_SH7367) || \ 706 defined(CONFIG_ARCH_SH7377) || \ 707 defined(CONFIG_ARCH_SH7372) || \ 708 defined(CONFIG_SH73A0) || \ 709 defined(CONFIG_R8A7740) 710 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 711 #elif defined(CONFIG_CPU_SH7723) ||\ 712 defined(CONFIG_CPU_SH7724) 713 static inline int scbrr_calc(struct uart_port port, int bps, int clk) 714 { 715 if (port.type == PORT_SCIF) 716 return (clk+16*bps)/(32*bps)-1; 717 else 718 return ((clk*2)+16*bps)/(16*bps)-1; 719 } 720 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) 721 #elif defined(__H8300H__) || defined(__H8300S__) 722 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) 723 #else /* Generic SH */ 724 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 725 #endif 726