1 /* 2 * Copy and modify from linux/drivers/serial/sh-sci.h 3 */ 4 5 struct uart_port { 6 unsigned long iobase; /* in/out[bwl] */ 7 unsigned char *membase; /* read/write[bwl] */ 8 unsigned long mapbase; /* for ioremap */ 9 unsigned int type; /* port type */ 10 }; 11 12 #define PORT_SCI 52 13 #define PORT_SCIF 53 14 #define PORT_SCIFA 83 15 #define PORT_SCIFB 93 16 17 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 18 #include <asm/regs306x.h> 19 #endif 20 #if defined(CONFIG_H8S2678) 21 #include <asm/regs267x.h> 22 #endif 23 24 #if defined(CONFIG_CPU_SH7706) || \ 25 defined(CONFIG_CPU_SH7707) || \ 26 defined(CONFIG_CPU_SH7708) || \ 27 defined(CONFIG_CPU_SH7709) 28 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 29 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 30 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 31 #elif defined(CONFIG_CPU_SH7705) 32 # define SCIF0 0xA4400000 33 # define SCIF2 0xA4410000 34 # define SCSMR_Ir 0xA44A0000 35 # define IRDA_SCIF SCIF0 36 # define SCPCR 0xA4000116 37 # define SCPDR 0xA4000136 38 39 /* Set the clock source, 40 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 41 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 42 */ 43 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 44 #elif defined(CONFIG_CPU_SH7720) || \ 45 defined(CONFIG_CPU_SH7721) || \ 46 defined(CONFIG_ARCH_SH7367) || \ 47 defined(CONFIG_ARCH_SH7377) || \ 48 defined(CONFIG_ARCH_SH7372) 49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 50 # define PORT_PTCR 0xA405011EUL 51 # define PORT_PVCR 0xA4050122UL 52 # define SCIF_ORER 0x0200 /* overrun error bit */ 53 #elif defined(CONFIG_SH_RTS7751R2D) 54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 56 # define SCIF_ORER 0x0001 /* overrun error bit */ 57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 58 #elif defined(CONFIG_CPU_SH7750) || \ 59 defined(CONFIG_CPU_SH7750R) || \ 60 defined(CONFIG_CPU_SH7750S) || \ 61 defined(CONFIG_CPU_SH7091) || \ 62 defined(CONFIG_CPU_SH7751) || \ 63 defined(CONFIG_CPU_SH7751R) 64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */ 65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 66 # define SCIF_ORER 0x0001 /* overrun error bit */ 67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 70 #elif defined(CONFIG_CPU_SH7760) 71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 74 # define SCIF_ORER 0x0001 /* overrun error bit */ 75 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 77 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 78 # define SCIF_ORER 0x0001 /* overrun error bit */ 79 # define PACR 0xa4050100 80 # define PBCR 0xa4050102 81 # define SCSCR_INIT(port) 0x3B 82 #elif defined(CONFIG_CPU_SH7343) 83 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 84 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 85 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 86 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 87 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 88 #elif defined(CONFIG_CPU_SH7722) 89 # define PADR 0xA4050120 90 # undef PSDR 91 # define PSDR 0xA405013e 92 # define PWDR 0xA4050166 93 # define PSCR 0xA405011E 94 # define SCIF_ORER 0x0001 /* overrun error bit */ 95 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 96 #elif defined(CONFIG_CPU_SH7366) 97 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 98 # define SCSPTR0 SCPDR0 99 # define SCIF_ORER 0x0001 /* overrun error bit */ 100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 101 #elif defined(CONFIG_CPU_SH7723) 102 # define SCSPTR0 0xa4050160 103 # define SCSPTR1 0xa405013e 104 # define SCSPTR2 0xa4050160 105 # define SCSPTR3 0xa405013e 106 # define SCSPTR4 0xa4050128 107 # define SCSPTR5 0xa4050128 108 # define SCIF_ORER 0x0001 /* overrun error bit */ 109 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 110 #elif defined(CONFIG_CPU_SH7724) 111 # define SCIF_ORER 0x0001 /* overrun error bit */ 112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 115 #elif defined(CONFIG_CPU_SH7734) 116 # define SCSPTR0 0xFFE40020 117 # define SCSPTR1 0xFFE41020 118 # define SCSPTR2 0xFFE42020 119 # define SCSPTR3 0xFFE43020 120 # define SCSPTR4 0xFFE44020 121 # define SCSPTR5 0xFFE45020 122 # define SCIF_ORER 0x0001 /* overrun error bit */ 123 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 124 #elif defined(CONFIG_CPU_SH4_202) 125 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 126 # define SCIF_ORER 0x0001 /* overrun error bit */ 127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 128 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) 129 # define SCIF_BASE_ADDR 0x01030000 130 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) 131 # define SCIF_PTR2_OFFS 0x0000020 132 # define SCIF_LSR2_OFFS 0x0000024 133 # define SCSPTR\ 134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 135 # define SCLSR2\ 136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 137 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 138 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 139 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 140 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 141 #elif defined(CONFIG_H8S2678) 142 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 143 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 144 #elif defined(CONFIG_CPU_SH7757) 145 # define SCSPTR0 0xfe4b0020 146 # define SCSPTR1 0xfe4b0020 147 # define SCSPTR2 0xfe4b0020 148 # define SCIF_ORER 0x0001 149 # define SCSCR_INIT(port) 0x38 150 # define SCIF_ONLY 151 #elif defined(CONFIG_CPU_SH7763) 152 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 153 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 154 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 155 # define SCIF_ORER 0x0001 /* overrun error bit */ 156 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 157 #elif defined(CONFIG_CPU_SH7770) 158 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 159 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 160 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 161 # define SCIF_ORER 0x0001 /* overrun error bit */ 162 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 163 #elif defined(CONFIG_CPU_SH7780) 164 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 165 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 166 # define SCIF_ORER 0x0001 /* Overrun error bit */ 167 168 #if defined(CONFIG_SH_SH2007) 169 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ 170 # define SCSCR_INIT(port) 0x38 171 #else 172 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ 173 # define SCSCR_INIT(port) 0x3a 174 #endif 175 176 #elif defined(CONFIG_CPU_SH7785) || \ 177 defined(CONFIG_CPU_SH7786) 178 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 179 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 180 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 181 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 182 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 183 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 184 # define SCIF_ORER 0x0001 /* Overrun error bit */ 185 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 186 #elif defined(CONFIG_CPU_SH7201) || \ 187 defined(CONFIG_CPU_SH7203) || \ 188 defined(CONFIG_CPU_SH7206) || \ 189 defined(CONFIG_CPU_SH7263) || \ 190 defined(CONFIG_CPU_SH7264) 191 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 192 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 193 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 194 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 195 # if defined(CONFIG_CPU_SH7201) 196 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 197 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 198 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 199 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 200 # endif 201 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 202 #elif defined(CONFIG_CPU_SH7619) 203 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 204 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 205 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 206 # define SCIF_ORER 0x0001 /* overrun error bit */ 207 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 208 #elif defined(CONFIG_CPU_SHX3) 209 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 210 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 211 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 212 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 213 # define SCIF_ORER 0x0001 /* Overrun error bit */ 214 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 215 #else 216 # error CPU subtype not defined 217 #endif 218 219 /* SCSCR */ 220 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 221 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 222 #define SCI_CTRL_FLAGS_TE 0x20 /* all */ 223 #define SCI_CTRL_FLAGS_RE 0x10 /* all */ 224 #if defined(CONFIG_CPU_SH7750) || \ 225 defined(CONFIG_CPU_SH7091) || \ 226 defined(CONFIG_CPU_SH7750R) || \ 227 defined(CONFIG_CPU_SH7722) || \ 228 defined(CONFIG_CPU_SH7734) || \ 229 defined(CONFIG_CPU_SH7750S) || \ 230 defined(CONFIG_CPU_SH7751) || \ 231 defined(CONFIG_CPU_SH7751R) || \ 232 defined(CONFIG_CPU_SH7763) || \ 233 defined(CONFIG_CPU_SH7780) || \ 234 defined(CONFIG_CPU_SH7785) || \ 235 defined(CONFIG_CPU_SH7786) || \ 236 defined(CONFIG_CPU_SHX3) 237 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 238 #elif defined(CONFIG_CPU_SH7724) 239 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) 240 #else 241 #define SCI_CTRL_FLAGS_REIE 0 242 #endif 243 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 244 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 245 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 246 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 247 248 /* SCxSR SCI */ 249 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 250 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 251 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 252 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 253 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 254 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 255 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 256 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 257 258 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 259 260 /* SCxSR SCIF */ 261 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 262 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 263 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 264 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 265 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 266 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 267 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 268 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 269 270 #if defined(CONFIG_CPU_SH7705) || \ 271 defined(CONFIG_CPU_SH7720) || \ 272 defined(CONFIG_CPU_SH7721) || \ 273 defined(CONFIG_ARCH_SH7367) || \ 274 defined(CONFIG_ARCH_SH7377) || \ 275 defined(CONFIG_ARCH_SH7372) 276 # define SCIF_ORER 0x0200 277 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 278 # define SCIF_RFDC_MASK 0x007f 279 # define SCIF_TXROOM_MAX 64 280 #elif defined(CONFIG_CPU_SH7763) 281 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 282 # define SCIF_RFDC_MASK 0x007f 283 # define SCIF_TXROOM_MAX 64 284 /* SH7763 SCIF2 support */ 285 # define SCIF2_RFDC_MASK 0x001f 286 # define SCIF2_TXROOM_MAX 16 287 #else 288 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 289 # define SCIF_RFDC_MASK 0x001f 290 # define SCIF_TXROOM_MAX 16 291 #endif 292 293 #ifndef SCIF_ORER 294 #define SCIF_ORER 0x0000 295 #endif 296 297 #define SCxSR_TEND(port)\ 298 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 299 #define SCxSR_ERRORS(port)\ 300 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 301 #define SCxSR_RDxF(port)\ 302 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 303 #define SCxSR_TDxE(port)\ 304 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 305 #define SCxSR_FER(port)\ 306 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 307 #define SCxSR_PER(port)\ 308 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 309 #define SCxSR_BRK(port)\ 310 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 311 #define SCxSR_ORER(port)\ 312 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 313 314 #if defined(CONFIG_CPU_SH7705) || \ 315 defined(CONFIG_CPU_SH7720) || \ 316 defined(CONFIG_CPU_SH7721) || \ 317 defined(CONFIG_ARCH_SH7367) || \ 318 defined(CONFIG_ARCH_SH7377) || \ 319 defined(CONFIG_ARCH_SH7372) 320 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 321 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 322 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 323 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 324 #else 325 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 326 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 327 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 328 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 329 #endif 330 331 /* SCFCR */ 332 #define SCFCR_RFRST 0x0002 333 #define SCFCR_TFRST 0x0004 334 #define SCFCR_TCRST 0x4000 335 #define SCFCR_MCE 0x0008 336 337 #define SCI_MAJOR 204 338 #define SCI_MINOR_START 8 339 340 /* Generic serial flags */ 341 #define SCI_RX_THROTTLE 0x0000001 342 343 #define SCI_MAGIC 0xbabeface 344 345 /* 346 * Events are used to schedule things to happen at timer-interrupt 347 * time, instead of at rs interrupt time. 348 */ 349 #define SCI_EVENT_WRITE_WAKEUP 0 350 351 #define SCI_IN(size, offset)\ 352 if ((size) == 8) {\ 353 return readb(port->membase + (offset));\ 354 } else {\ 355 return readw(port->membase + (offset));\ 356 } 357 #define SCI_OUT(size, offset, value)\ 358 if ((size) == 8) {\ 359 writeb(value, port->membase + (offset));\ 360 } else if ((size) == 16) {\ 361 writew(value, port->membase + (offset));\ 362 } 363 364 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 365 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 366 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 367 SCI_IN(scif_size, scif_offset)\ 368 } else { /* PORT_SCI or PORT_SCIFA */\ 369 SCI_IN(sci_size, sci_offset);\ 370 }\ 371 }\ 372 static inline void sci_##name##_out(struct uart_port *port,\ 373 unsigned int value) {\ 374 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 375 SCI_OUT(scif_size, scif_offset, value)\ 376 } else { /* PORT_SCI or PORT_SCIFA */\ 377 SCI_OUT(sci_size, sci_offset, value);\ 378 }\ 379 } 380 381 #ifdef CONFIG_H8300 382 /* h8300 don't have SCIF */ 383 #define CPU_SCIF_FNS(name) \ 384 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 385 return 0;\ 386 }\ 387 static inline void sci_##name##_out(struct uart_port *port,\ 388 unsigned int value) {\ 389 } 390 #else 391 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 392 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 393 SCI_IN(scif_size, scif_offset);\ 394 }\ 395 static inline void sci_##name##_out(struct uart_port *port,\ 396 unsigned int value) {\ 397 SCI_OUT(scif_size, scif_offset, value);\ 398 } 399 #endif 400 401 #define CPU_SCI_FNS(name, sci_offset, sci_size)\ 402 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 403 SCI_IN(sci_size, sci_offset);\ 404 }\ 405 static inline void sci_##name##_out(struct uart_port *port,\ 406 unsigned int value) {\ 407 SCI_OUT(sci_size, sci_offset, value);\ 408 } 409 410 #if defined(CONFIG_SH3) || \ 411 defined(CONFIG_ARCH_SH7367) || \ 412 defined(CONFIG_ARCH_SH7377) || \ 413 defined(CONFIG_ARCH_SH7372) 414 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 415 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 416 sh4_sci_offset, sh4_sci_size, \ 417 sh3_scif_offset, sh3_scif_size, \ 418 sh4_scif_offset, sh4_scif_size, \ 419 h8_sci_offset, h8_sci_size) \ 420 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 421 sh4_scif_offset, sh4_scif_size) 422 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 423 sh4_scif_offset, sh4_scif_size) \ 424 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 425 #elif defined(CONFIG_CPU_SH7705) || \ 426 defined(CONFIG_CPU_SH7720) || \ 427 defined(CONFIG_CPU_SH7721) || \ 428 defined(CONFIG_ARCH_SH7367) || \ 429 defined(CONFIG_ARCH_SH7377) 430 #define SCIF_FNS(name, scif_offset, scif_size) \ 431 CPU_SCIF_FNS(name, scif_offset, scif_size) 432 #elif defined(CONFIG_ARCH_SH7372) 433 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 434 sh4_scifb_offset, sh4_scifb_size) \ 435 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 436 sh4_scifb_offset, sh4_scifb_size) 437 #define SCIF_FNS(name, scif_offset, scif_size) \ 438 CPU_SCIF_FNS(name, scif_offset, scif_size) 439 #else 440 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 441 sh4_sci_offset, sh4_sci_size, \ 442 sh3_scif_offset, sh3_scif_size,\ 443 sh4_scif_offset, sh4_scif_size, \ 444 h8_sci_offset, h8_sci_size) \ 445 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 446 sh3_scif_offset, sh3_scif_size) 447 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 448 sh4_scif_offset, sh4_scif_size) \ 449 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 450 #endif 451 #elif defined(__H8300H__) || defined(__H8300S__) 452 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 453 sh4_sci_offset, sh4_sci_size, \ 454 sh3_scif_offset, sh3_scif_size,\ 455 sh4_scif_offset, sh4_scif_size, \ 456 h8_sci_offset, h8_sci_size) \ 457 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 458 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 459 sh4_scif_offset, sh4_scif_size) \ 460 CPU_SCIF_FNS(name) 461 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) 462 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 463 sh4_scif_offset, sh4_scif_size) \ 464 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 465 sh4_scif_offset, sh4_scif_size) 466 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 467 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 468 #else 469 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 470 sh4_sci_offset, sh4_sci_size, \ 471 sh3_scif_offset, sh3_scif_size,\ 472 sh4_scif_offset, sh4_scif_size, \ 473 h8_sci_offset, h8_sci_size) \ 474 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 475 sh4_scif_offset, sh4_scif_size) 476 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ 477 sh4_scif_offset, sh4_scif_size) \ 478 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 479 #endif 480 481 #if defined(CONFIG_CPU_SH7705) || \ 482 defined(CONFIG_CPU_SH7720) || \ 483 defined(CONFIG_CPU_SH7721) || \ 484 defined(CONFIG_ARCH_SH7367) || \ 485 defined(CONFIG_ARCH_SH7377) 486 487 SCIF_FNS(SCSMR, 0x00, 16) 488 SCIF_FNS(SCBRR, 0x04, 8) 489 SCIF_FNS(SCSCR, 0x08, 16) 490 SCIF_FNS(SCTDSR, 0x0c, 8) 491 SCIF_FNS(SCFER, 0x10, 16) 492 SCIF_FNS(SCxSR, 0x14, 16) 493 SCIF_FNS(SCFCR, 0x18, 16) 494 SCIF_FNS(SCFDR, 0x1c, 16) 495 SCIF_FNS(SCxTDR, 0x20, 8) 496 SCIF_FNS(SCxRDR, 0x24, 8) 497 SCIF_FNS(SCLSR, 0x00, 0) 498 #elif defined(CONFIG_ARCH_SH7372) 499 SCIF_FNS(SCSMR, 0x00, 16) 500 SCIF_FNS(SCBRR, 0x04, 8) 501 SCIF_FNS(SCSCR, 0x08, 16) 502 SCIF_FNS(SCTDSR, 0x0c, 16) 503 SCIF_FNS(SCFER, 0x10, 16) 504 SCIF_FNS(SCxSR, 0x14, 16) 505 SCIF_FNS(SCFCR, 0x18, 16) 506 SCIF_FNS(SCFDR, 0x1c, 16) 507 SCIF_FNS(SCTFDR, 0x38, 16) 508 SCIF_FNS(SCRFDR, 0x3c, 16) 509 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 510 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 511 SCIF_FNS(SCLSR, 0x00, 0) 512 #elif defined(CONFIG_CPU_SH7723) ||\ 513 defined(CONFIG_CPU_SH7724) 514 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 515 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 516 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 517 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 518 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 519 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 520 SCIx_FNS(SCSPTR, 0, 0, 0, 0) 521 SCIF_FNS(SCTDSR, 0x0c, 8) 522 SCIF_FNS(SCFER, 0x10, 16) 523 SCIF_FNS(SCFCR, 0x18, 16) 524 SCIF_FNS(SCFDR, 0x1c, 16) 525 SCIF_FNS(SCLSR, 0x24, 16) 526 #else 527 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 528 /* name off sz off sz off sz off sz off sz*/ 529 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 530 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 531 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 532 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 533 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 534 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 535 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 536 #if defined(CONFIG_CPU_SH7760) || \ 537 defined(CONFIG_CPU_SH7780) || \ 538 defined(CONFIG_CPU_SH7785) || \ 539 defined(CONFIG_CPU_SH7786) 540 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 541 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 542 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 543 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 544 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 545 #elif defined(CONFIG_CPU_SH7763) 546 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 547 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 548 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) 549 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 550 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 551 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 552 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 553 #else 554 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 555 #if defined(CONFIG_CPU_SH7722) 556 SCIF_FNS(SCSPTR, 0, 0, 0, 0) 557 #else 558 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 559 #endif 560 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 561 #endif 562 #endif 563 #define sci_in(port, reg) sci_##reg##_in(port) 564 #define sci_out(port, reg, value) sci_##reg##_out(port, value) 565 566 /* H8/300 series SCI pins assignment */ 567 #if defined(__H8300H__) || defined(__H8300S__) 568 static const struct __attribute__((packed)) { 569 int port; /* GPIO port no */ 570 unsigned short rx, tx; /* GPIO bit no */ 571 } h8300_sci_pins[] = { 572 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 573 { /* SCI0 */ 574 .port = H8300_GPIO_P9, 575 .rx = H8300_GPIO_B2, 576 .tx = H8300_GPIO_B0, 577 }, 578 { /* SCI1 */ 579 .port = H8300_GPIO_P9, 580 .rx = H8300_GPIO_B3, 581 .tx = H8300_GPIO_B1, 582 }, 583 { /* SCI2 */ 584 .port = H8300_GPIO_PB, 585 .rx = H8300_GPIO_B7, 586 .tx = H8300_GPIO_B6, 587 } 588 #elif defined(CONFIG_H8S2678) 589 { /* SCI0 */ 590 .port = H8300_GPIO_P3, 591 .rx = H8300_GPIO_B2, 592 .tx = H8300_GPIO_B0, 593 }, 594 { /* SCI1 */ 595 .port = H8300_GPIO_P3, 596 .rx = H8300_GPIO_B3, 597 .tx = H8300_GPIO_B1, 598 }, 599 { /* SCI2 */ 600 .port = H8300_GPIO_P5, 601 .rx = H8300_GPIO_B1, 602 .tx = H8300_GPIO_B0, 603 } 604 #endif 605 }; 606 #endif 607 608 #if defined(CONFIG_CPU_SH7706) || \ 609 defined(CONFIG_CPU_SH7707) || \ 610 defined(CONFIG_CPU_SH7708) || \ 611 defined(CONFIG_CPU_SH7709) 612 static inline int sci_rxd_in(struct uart_port *port) 613 { 614 if (port->mapbase == 0xfffffe80) 615 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 616 return 1; 617 } 618 #elif defined(CONFIG_CPU_SH7750) || \ 619 defined(CONFIG_CPU_SH7751) || \ 620 defined(CONFIG_CPU_SH7751R) || \ 621 defined(CONFIG_CPU_SH7750R) || \ 622 defined(CONFIG_CPU_SH7750S) || \ 623 defined(CONFIG_CPU_SH7091) 624 static inline int sci_rxd_in(struct uart_port *port) 625 { 626 if (port->mapbase == 0xffe00000) 627 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 628 return 1; 629 } 630 #elif defined(__H8300H__) || defined(__H8300S__) 631 static inline int sci_rxd_in(struct uart_port *port) 632 { 633 int ch = (port->mapbase - SMR0) >> 3; 634 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 635 } 636 #else /* default case for non-SCI processors */ 637 static inline int sci_rxd_in(struct uart_port *port) 638 { 639 return 1; 640 } 641 #endif 642 643 /* 644 * Values for the BitRate Register (SCBRR) 645 * 646 * The values are actually divisors for a frequency which can 647 * be internal to the SH3 (14.7456MHz) or derived from an external 648 * clock source. This driver assumes the internal clock is used; 649 * to support using an external clock source, config options or 650 * possibly command-line options would need to be added. 651 * 652 * Also, to support speeds below 2400 (why?) the lower 2 bits of 653 * the SCSMR register would also need to be set to non-zero values. 654 * 655 * -- Greg Banks 27Feb2000 656 * 657 * Answer: The SCBRR register is only eight bits, and the value in 658 * it gets larger with lower baud rates. At around 2400 (depending on 659 * the peripherial module clock) you run out of bits. However the 660 * lower two bits of SCSMR allow the module clock to be divided down, 661 * scaling the value which is needed in SCBRR. 662 * 663 * -- Stuart Menefy - 23 May 2000 664 * 665 * I meant, why would anyone bother with bitrates below 2400. 666 * 667 * -- Greg Banks - 7Jul2000 668 * 669 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 670 * tape reader as a console! 671 * 672 * -- Mitch Davis - 15 Jul 2000 673 */ 674 675 #if (defined(CONFIG_CPU_SH7780) || \ 676 defined(CONFIG_CPU_SH7785) || \ 677 defined(CONFIG_CPU_SH7786)) && \ 678 !defined(CONFIG_SH_SH2007) 679 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 680 #elif defined(CONFIG_CPU_SH7705) || \ 681 defined(CONFIG_CPU_SH7720) || \ 682 defined(CONFIG_CPU_SH7721) || \ 683 defined(CONFIG_ARCH_SH7367) || \ 684 defined(CONFIG_ARCH_SH7377) || \ 685 defined(CONFIG_ARCH_SH7372) 686 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 687 #elif defined(CONFIG_CPU_SH7723) ||\ 688 defined(CONFIG_CPU_SH7724) 689 static inline int scbrr_calc(struct uart_port port, int bps, int clk) 690 { 691 if (port.type == PORT_SCIF) 692 return (clk+16*bps)/(32*bps)-1; 693 else 694 return ((clk*2)+16*bps)/(16*bps)-1; 695 } 696 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) 697 #elif defined(__H8300H__) || defined(__H8300S__) 698 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) 699 #else /* Generic SH */ 700 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 701 #endif 702