1 /* 2 * Copy and modify from linux/drivers/serial/sh-sci.h 3 */ 4 5 #include <dm/platform_data/serial_sh.h> 6 7 struct uart_port { 8 unsigned long iobase; /* in/out[bwl] */ 9 unsigned char *membase; /* read/write[bwl] */ 10 unsigned long mapbase; /* for ioremap */ 11 enum sh_serial_type type; /* port type */ 12 enum sh_clk_mode clk_mode; /* clock mode */ 13 }; 14 15 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 16 #include <asm/regs306x.h> 17 #endif 18 #if defined(CONFIG_H8S2678) 19 #include <asm/regs267x.h> 20 #endif 21 22 #if defined(CONFIG_CPU_SH7706) || \ 23 defined(CONFIG_CPU_SH7707) || \ 24 defined(CONFIG_CPU_SH7708) || \ 25 defined(CONFIG_CPU_SH7709) 26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 27 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 28 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 29 #elif defined(CONFIG_CPU_SH7705) 30 # define SCIF0 0xA4400000 31 # define SCIF2 0xA4410000 32 # define SCSMR_Ir 0xA44A0000 33 # define IRDA_SCIF SCIF0 34 # define SCPCR 0xA4000116 35 # define SCPDR 0xA4000136 36 37 /* Set the clock source, 38 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 39 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 40 */ 41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 42 #elif defined(CONFIG_CPU_SH7720) || \ 43 defined(CONFIG_CPU_SH7721) || \ 44 defined(CONFIG_ARCH_SH7367) || \ 45 defined(CONFIG_ARCH_SH7377) || \ 46 defined(CONFIG_ARCH_SH7372) || \ 47 defined(CONFIG_SH73A0) || \ 48 defined(CONFIG_R8A7740) 49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 50 # define PORT_PTCR 0xA405011EUL 51 # define PORT_PVCR 0xA4050122UL 52 # define SCIF_ORER 0x0200 /* overrun error bit */ 53 #elif defined(CONFIG_SH_RTS7751R2D) 54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 56 # define SCIF_ORER 0x0001 /* overrun error bit */ 57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 58 #elif defined(CONFIG_CPU_SH7750) || \ 59 defined(CONFIG_CPU_SH7750R) || \ 60 defined(CONFIG_CPU_SH7750S) || \ 61 defined(CONFIG_CPU_SH7091) || \ 62 defined(CONFIG_CPU_SH7751) || \ 63 defined(CONFIG_CPU_SH7751R) 64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */ 65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 66 # define SCIF_ORER 0x0001 /* overrun error bit */ 67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 70 #elif defined(CONFIG_CPU_SH7760) 71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 74 # define SCIF_ORER 0x0001 /* overrun error bit */ 75 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 77 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 78 # define SCIF_ORER 0x0001 /* overrun error bit */ 79 # define PACR 0xa4050100 80 # define PBCR 0xa4050102 81 # define SCSCR_INIT(port) 0x3B 82 #elif defined(CONFIG_CPU_SH7343) 83 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 84 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 85 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 86 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 87 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 88 #elif defined(CONFIG_CPU_SH7722) 89 # define PADR 0xA4050120 90 # undef PSDR 91 # define PSDR 0xA405013e 92 # define PWDR 0xA4050166 93 # define PSCR 0xA405011E 94 # define SCIF_ORER 0x0001 /* overrun error bit */ 95 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 96 #elif defined(CONFIG_CPU_SH7366) 97 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 98 # define SCSPTR0 SCPDR0 99 # define SCIF_ORER 0x0001 /* overrun error bit */ 100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 101 #elif defined(CONFIG_CPU_SH7723) 102 # define SCSPTR0 0xa4050160 103 # define SCSPTR1 0xa405013e 104 # define SCSPTR2 0xa4050160 105 # define SCSPTR3 0xa405013e 106 # define SCSPTR4 0xa4050128 107 # define SCSPTR5 0xa4050128 108 # define SCIF_ORER 0x0001 /* overrun error bit */ 109 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 110 #elif defined(CONFIG_CPU_SH7724) 111 # define SCIF_ORER 0x0001 /* overrun error bit */ 112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 115 #elif defined(CONFIG_CPU_SH7734) 116 # define SCSPTR0 0xFFE40020 117 # define SCSPTR1 0xFFE41020 118 # define SCSPTR2 0xFFE42020 119 # define SCSPTR3 0xFFE43020 120 # define SCSPTR4 0xFFE44020 121 # define SCSPTR5 0xFFE45020 122 # define SCIF_ORER 0x0001 /* overrun error bit */ 123 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 124 #elif defined(CONFIG_CPU_SH4_202) 125 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 126 # define SCIF_ORER 0x0001 /* overrun error bit */ 127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 128 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) 129 # define SCIF_BASE_ADDR 0x01030000 130 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) 131 # define SCIF_PTR2_OFFS 0x0000020 132 # define SCIF_LSR2_OFFS 0x0000024 133 # define SCSPTR\ 134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 135 # define SCLSR2\ 136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 137 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 138 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 139 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 140 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 141 #elif defined(CONFIG_H8S2678) 142 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 143 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 144 #elif defined(CONFIG_CPU_SH7757) || \ 145 defined(CONFIG_CPU_SH7752) || \ 146 defined(CONFIG_CPU_SH7753) 147 # define SCSPTR0 0xfe4b0020 148 # define SCSPTR1 0xfe4b0020 149 # define SCSPTR2 0xfe4b0020 150 # define SCIF_ORER 0x0001 151 # define SCSCR_INIT(port) 0x38 152 # define SCIF_ONLY 153 #elif defined(CONFIG_CPU_SH7763) 154 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 155 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 156 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 157 # define SCIF_ORER 0x0001 /* overrun error bit */ 158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 159 #elif defined(CONFIG_CPU_SH7770) 160 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 161 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 162 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 163 # define SCIF_ORER 0x0001 /* overrun error bit */ 164 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 165 #elif defined(CONFIG_CPU_SH7780) 166 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 167 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 168 # define SCIF_ORER 0x0001 /* Overrun error bit */ 169 170 #if defined(CONFIG_SH_SH2007) 171 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ 172 # define SCSCR_INIT(port) 0x38 173 #else 174 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ 175 # define SCSCR_INIT(port) 0x3a 176 #endif 177 178 #elif defined(CONFIG_CPU_SH7785) || \ 179 defined(CONFIG_CPU_SH7786) 180 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 181 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 182 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 183 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 184 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 185 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 186 # define SCIF_ORER 0x0001 /* Overrun error bit */ 187 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 188 #elif defined(CONFIG_CPU_SH7201) || \ 189 defined(CONFIG_CPU_SH7203) || \ 190 defined(CONFIG_CPU_SH7206) || \ 191 defined(CONFIG_CPU_SH7263) || \ 192 defined(CONFIG_CPU_SH7264) 193 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 194 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 195 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 196 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 197 # if defined(CONFIG_CPU_SH7201) 198 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 199 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 200 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 201 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 202 # endif 203 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 204 #elif defined(CONFIG_CPU_SH7269) 205 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ 206 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ 207 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ 208 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */ 209 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */ 210 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */ 211 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ 212 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ 213 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 214 #elif defined(CONFIG_CPU_SH7619) 215 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 216 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 217 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 218 # define SCIF_ORER 0x0001 /* overrun error bit */ 219 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 220 #elif defined(CONFIG_CPU_SHX3) 221 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 222 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 223 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 224 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 225 # define SCIF_ORER 0x0001 /* Overrun error bit */ 226 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 227 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 228 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 229 # define SCIF_ORER 0x0001 230 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) 231 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ 232 #else 233 # error CPU subtype not defined 234 #endif 235 236 /* SCSCR */ 237 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 238 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 239 #define SCI_CTRL_FLAGS_TE 0x20 /* all */ 240 #define SCI_CTRL_FLAGS_RE 0x10 /* all */ 241 #if defined(CONFIG_CPU_SH7750) || \ 242 defined(CONFIG_CPU_SH7091) || \ 243 defined(CONFIG_CPU_SH7750R) || \ 244 defined(CONFIG_CPU_SH7722) || \ 245 defined(CONFIG_CPU_SH7734) || \ 246 defined(CONFIG_CPU_SH7750S) || \ 247 defined(CONFIG_CPU_SH7751) || \ 248 defined(CONFIG_CPU_SH7751R) || \ 249 defined(CONFIG_CPU_SH7763) || \ 250 defined(CONFIG_CPU_SH7780) || \ 251 defined(CONFIG_CPU_SH7785) || \ 252 defined(CONFIG_CPU_SH7786) || \ 253 defined(CONFIG_CPU_SHX3) 254 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 255 #elif defined(CONFIG_CPU_SH7724) 256 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) 257 #else 258 #define SCI_CTRL_FLAGS_REIE 0 259 #endif 260 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 261 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 262 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 263 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 264 265 /* SCxSR SCI */ 266 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 267 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 268 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 269 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 270 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 271 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 272 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 273 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 274 275 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 276 277 /* SCxSR SCIF */ 278 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 279 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 280 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 281 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 282 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 283 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 284 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 285 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 286 287 #if defined(CONFIG_CPU_SH7705) || \ 288 defined(CONFIG_CPU_SH7720) || \ 289 defined(CONFIG_CPU_SH7721) || \ 290 defined(CONFIG_ARCH_SH7367) || \ 291 defined(CONFIG_ARCH_SH7377) || \ 292 defined(CONFIG_ARCH_SH7372) || \ 293 defined(CONFIG_SH73A0) || \ 294 defined(CONFIG_R8A7740) 295 # define SCIF_ORER 0x0200 296 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 297 # define SCIF_RFDC_MASK 0x007f 298 # define SCIF_TXROOM_MAX 64 299 #elif defined(CONFIG_CPU_SH7763) 300 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 301 # define SCIF_RFDC_MASK 0x007f 302 # define SCIF_TXROOM_MAX 64 303 /* SH7763 SCIF2 support */ 304 # define SCIF2_RFDC_MASK 0x001f 305 # define SCIF2_TXROOM_MAX 16 306 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 307 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 308 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 309 # define SCIF_RFDC_MASK 0x003f 310 #else 311 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 312 # define SCIF_RFDC_MASK 0x001f 313 # define SCIF_TXROOM_MAX 16 314 #endif 315 316 #ifndef SCIF_ORER 317 #define SCIF_ORER 0x0000 318 #endif 319 320 #define SCxSR_TEND(port)\ 321 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 322 #define SCxSR_ERRORS(port)\ 323 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 324 #define SCxSR_RDxF(port)\ 325 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 326 #define SCxSR_TDxE(port)\ 327 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 328 #define SCxSR_FER(port)\ 329 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 330 #define SCxSR_PER(port)\ 331 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 332 #define SCxSR_BRK(port)\ 333 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 334 #define SCxSR_ORER(port)\ 335 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 336 337 #if defined(CONFIG_CPU_SH7705) || \ 338 defined(CONFIG_CPU_SH7720) || \ 339 defined(CONFIG_CPU_SH7721) || \ 340 defined(CONFIG_ARCH_SH7367) || \ 341 defined(CONFIG_ARCH_SH7377) || \ 342 defined(CONFIG_ARCH_SH7372) || \ 343 defined(CONFIG_SH73A0) || \ 344 defined(CONFIG_R8A7740) 345 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 346 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 347 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 348 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 349 #else 350 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 351 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 352 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 353 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 354 #endif 355 356 /* SCFCR */ 357 #define SCFCR_RFRST 0x0002 358 #define SCFCR_TFRST 0x0004 359 #define SCFCR_TCRST 0x4000 360 #define SCFCR_MCE 0x0008 361 362 #define SCI_MAJOR 204 363 #define SCI_MINOR_START 8 364 365 /* Generic serial flags */ 366 #define SCI_RX_THROTTLE 0x0000001 367 368 #define SCI_MAGIC 0xbabeface 369 370 /* 371 * Events are used to schedule things to happen at timer-interrupt 372 * time, instead of at rs interrupt time. 373 */ 374 #define SCI_EVENT_WRITE_WAKEUP 0 375 376 #define SCI_IN(size, offset)\ 377 if ((size) == 8) {\ 378 return readb(port->membase + (offset));\ 379 } else {\ 380 return readw(port->membase + (offset));\ 381 } 382 #define SCI_OUT(size, offset, value)\ 383 if ((size) == 8) {\ 384 writeb(value, port->membase + (offset));\ 385 } else if ((size) == 16) {\ 386 writew(value, port->membase + (offset));\ 387 } 388 389 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 390 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 391 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 392 SCI_IN(scif_size, scif_offset)\ 393 } else { /* PORT_SCI or PORT_SCIFA */\ 394 SCI_IN(sci_size, sci_offset);\ 395 }\ 396 }\ 397 static inline void sci_##name##_out(struct uart_port *port,\ 398 unsigned int value) {\ 399 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 400 SCI_OUT(scif_size, scif_offset, value)\ 401 } else { /* PORT_SCI or PORT_SCIFA */\ 402 SCI_OUT(sci_size, sci_offset, value);\ 403 }\ 404 } 405 406 #ifdef CONFIG_H8300 407 /* h8300 don't have SCIF */ 408 #define CPU_SCIF_FNS(name) \ 409 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 410 return 0;\ 411 }\ 412 static inline void sci_##name##_out(struct uart_port *port,\ 413 unsigned int value) {\ 414 } 415 #else 416 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 417 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 418 SCI_IN(scif_size, scif_offset);\ 419 }\ 420 static inline void sci_##name##_out(struct uart_port *port,\ 421 unsigned int value) {\ 422 SCI_OUT(scif_size, scif_offset, value);\ 423 } 424 #endif 425 426 #define CPU_SCI_FNS(name, sci_offset, sci_size)\ 427 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 428 SCI_IN(sci_size, sci_offset);\ 429 }\ 430 static inline void sci_##name##_out(struct uart_port *port,\ 431 unsigned int value) {\ 432 SCI_OUT(sci_size, sci_offset, value);\ 433 } 434 435 #if defined(CONFIG_CPU_SH3) || \ 436 defined(CONFIG_ARCH_SH7367) || \ 437 defined(CONFIG_ARCH_SH7377) || \ 438 defined(CONFIG_ARCH_SH7372) || \ 439 defined(CONFIG_SH73A0) || \ 440 defined(CONFIG_R8A7740) 441 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 442 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 443 sh4_sci_offset, sh4_sci_size, \ 444 sh3_scif_offset, sh3_scif_size, \ 445 sh4_scif_offset, sh4_scif_size, \ 446 h8_sci_offset, h8_sci_size) \ 447 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 448 sh4_scif_offset, sh4_scif_size) 449 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 450 sh4_scif_offset, sh4_scif_size) \ 451 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 452 #elif defined(CONFIG_CPU_SH7705) || \ 453 defined(CONFIG_CPU_SH7720) || \ 454 defined(CONFIG_CPU_SH7721) || \ 455 defined(CONFIG_ARCH_SH7367) || \ 456 defined(CONFIG_ARCH_SH7377) || \ 457 defined(CONFIG_SH73A0) 458 #define SCIF_FNS(name, scif_offset, scif_size) \ 459 CPU_SCIF_FNS(name, scif_offset, scif_size) 460 #elif defined(CONFIG_ARCH_SH7372) || \ 461 defined(CONFIG_R8A7740) 462 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 463 sh4_scifb_offset, sh4_scifb_size) \ 464 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 465 sh4_scifb_offset, sh4_scifb_size) 466 #define SCIF_FNS(name, scif_offset, scif_size) \ 467 CPU_SCIF_FNS(name, scif_offset, scif_size) 468 #else 469 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 470 sh4_sci_offset, sh4_sci_size, \ 471 sh3_scif_offset, sh3_scif_size,\ 472 sh4_scif_offset, sh4_scif_size, \ 473 h8_sci_offset, h8_sci_size) \ 474 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 475 sh3_scif_offset, sh3_scif_size) 476 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 477 sh4_scif_offset, sh4_scif_size) \ 478 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 479 #endif 480 #elif defined(__H8300H__) || defined(__H8300S__) 481 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 482 sh4_sci_offset, sh4_sci_size, \ 483 sh3_scif_offset, sh3_scif_size,\ 484 sh4_scif_offset, sh4_scif_size, \ 485 h8_sci_offset, h8_sci_size) \ 486 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 487 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 488 sh4_scif_offset, sh4_scif_size) \ 489 CPU_SCIF_FNS(name) 490 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) 491 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 492 sh4_scif_offset, sh4_scif_size) \ 493 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 494 sh4_scif_offset, sh4_scif_size) 495 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 496 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 497 #else 498 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 499 sh4_sci_offset, sh4_sci_size, \ 500 sh3_scif_offset, sh3_scif_size,\ 501 sh4_scif_offset, sh4_scif_size, \ 502 h8_sci_offset, h8_sci_size) \ 503 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 504 sh4_scif_offset, sh4_scif_size) 505 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ 506 sh4_scif_offset, sh4_scif_size) \ 507 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 508 #endif 509 510 #if defined(CONFIG_CPU_SH7705) || \ 511 defined(CONFIG_CPU_SH7720) || \ 512 defined(CONFIG_CPU_SH7721) || \ 513 defined(CONFIG_ARCH_SH7367) || \ 514 defined(CONFIG_ARCH_SH7377) || \ 515 defined(CONFIG_SH73A0) 516 517 SCIF_FNS(SCSMR, 0x00, 16) 518 SCIF_FNS(SCBRR, 0x04, 8) 519 SCIF_FNS(SCSCR, 0x08, 16) 520 SCIF_FNS(SCTDSR, 0x0c, 8) 521 SCIF_FNS(SCFER, 0x10, 16) 522 SCIF_FNS(SCxSR, 0x14, 16) 523 SCIF_FNS(SCFCR, 0x18, 16) 524 SCIF_FNS(SCFDR, 0x1c, 16) 525 SCIF_FNS(SCxTDR, 0x20, 8) 526 SCIF_FNS(SCxRDR, 0x24, 8) 527 SCIF_FNS(SCLSR, 0x00, 0) 528 SCIF_FNS(DL, 0x00, 0) /* dummy */ 529 #elif defined(CONFIG_ARCH_SH7372) || \ 530 defined(CONFIG_R8A7740) 531 SCIF_FNS(SCSMR, 0x00, 16) 532 SCIF_FNS(SCBRR, 0x04, 8) 533 SCIF_FNS(SCSCR, 0x08, 16) 534 SCIF_FNS(SCTDSR, 0x0c, 16) 535 SCIF_FNS(SCFER, 0x10, 16) 536 SCIF_FNS(SCxSR, 0x14, 16) 537 SCIF_FNS(SCFCR, 0x18, 16) 538 SCIF_FNS(SCFDR, 0x1c, 16) 539 SCIF_FNS(SCTFDR, 0x38, 16) 540 SCIF_FNS(SCRFDR, 0x3c, 16) 541 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 542 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 543 SCIF_FNS(SCLSR, 0x00, 0) 544 SCIF_FNS(DL, 0x00, 0) /* dummy */ 545 #elif defined(CONFIG_CPU_SH7723) ||\ 546 defined(CONFIG_CPU_SH7724) 547 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 548 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 549 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 550 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 551 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 552 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 553 SCIx_FNS(SCSPTR, 0, 0, 0, 0) 554 SCIF_FNS(SCTDSR, 0x0c, 8) 555 SCIF_FNS(SCFER, 0x10, 16) 556 SCIF_FNS(SCFCR, 0x18, 16) 557 SCIF_FNS(SCFDR, 0x1c, 16) 558 SCIF_FNS(SCLSR, 0x24, 16) 559 SCIF_FNS(DL, 0x00, 0) /* dummy */ 560 #else 561 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 562 /* name off sz off sz off sz off sz off sz*/ 563 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 564 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 565 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 566 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 567 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 568 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 569 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 570 #if defined(CONFIG_CPU_SH7760) || \ 571 defined(CONFIG_CPU_SH7780) || \ 572 defined(CONFIG_CPU_SH7785) || \ 573 defined(CONFIG_CPU_SH7786) 574 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 575 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 576 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 577 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 578 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 579 #elif defined(CONFIG_CPU_SH7763) 580 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 581 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 582 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) 583 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 584 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 585 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 586 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 587 #else 588 589 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 590 #if defined(CONFIG_CPU_SH7722) 591 SCIF_FNS(SCSPTR, 0, 0, 0, 0) 592 #else 593 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 594 #endif 595 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 596 #endif 597 #if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 598 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 599 SCIF_FNS(DL, 0, 0, 0x30, 16) 600 SCIF_FNS(CKS, 0, 0, 0x34, 16) 601 #else 602 SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ 603 #endif 604 #endif 605 #define sci_in(port, reg) sci_##reg##_in(port) 606 #define sci_out(port, reg, value) sci_##reg##_out(port, value) 607 608 /* H8/300 series SCI pins assignment */ 609 #if defined(__H8300H__) || defined(__H8300S__) 610 static const struct __attribute__((packed)) { 611 int port; /* GPIO port no */ 612 unsigned short rx, tx; /* GPIO bit no */ 613 } h8300_sci_pins[] = { 614 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 615 { /* SCI0 */ 616 .port = H8300_GPIO_P9, 617 .rx = H8300_GPIO_B2, 618 .tx = H8300_GPIO_B0, 619 }, 620 { /* SCI1 */ 621 .port = H8300_GPIO_P9, 622 .rx = H8300_GPIO_B3, 623 .tx = H8300_GPIO_B1, 624 }, 625 { /* SCI2 */ 626 .port = H8300_GPIO_PB, 627 .rx = H8300_GPIO_B7, 628 .tx = H8300_GPIO_B6, 629 } 630 #elif defined(CONFIG_H8S2678) 631 { /* SCI0 */ 632 .port = H8300_GPIO_P3, 633 .rx = H8300_GPIO_B2, 634 .tx = H8300_GPIO_B0, 635 }, 636 { /* SCI1 */ 637 .port = H8300_GPIO_P3, 638 .rx = H8300_GPIO_B3, 639 .tx = H8300_GPIO_B1, 640 }, 641 { /* SCI2 */ 642 .port = H8300_GPIO_P5, 643 .rx = H8300_GPIO_B1, 644 .tx = H8300_GPIO_B0, 645 } 646 #endif 647 }; 648 #endif 649 650 #if defined(CONFIG_CPU_SH7706) || \ 651 defined(CONFIG_CPU_SH7707) || \ 652 defined(CONFIG_CPU_SH7708) || \ 653 defined(CONFIG_CPU_SH7709) 654 static inline int sci_rxd_in(struct uart_port *port) 655 { 656 if (port->mapbase == 0xfffffe80) 657 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 658 return 1; 659 } 660 #elif defined(CONFIG_CPU_SH7750) || \ 661 defined(CONFIG_CPU_SH7751) || \ 662 defined(CONFIG_CPU_SH7751R) || \ 663 defined(CONFIG_CPU_SH7750R) || \ 664 defined(CONFIG_CPU_SH7750S) || \ 665 defined(CONFIG_CPU_SH7091) 666 static inline int sci_rxd_in(struct uart_port *port) 667 { 668 if (port->mapbase == 0xffe00000) 669 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 670 return 1; 671 } 672 #elif defined(__H8300H__) || defined(__H8300S__) 673 static inline int sci_rxd_in(struct uart_port *port) 674 { 675 int ch = (port->mapbase - SMR0) >> 3; 676 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 677 } 678 #else /* default case for non-SCI processors */ 679 static inline int sci_rxd_in(struct uart_port *port) 680 { 681 return 1; 682 } 683 #endif 684 685 /* 686 * Values for the BitRate Register (SCBRR) 687 * 688 * The values are actually divisors for a frequency which can 689 * be internal to the SH3 (14.7456MHz) or derived from an external 690 * clock source. This driver assumes the internal clock is used; 691 * to support using an external clock source, config options or 692 * possibly command-line options would need to be added. 693 * 694 * Also, to support speeds below 2400 (why?) the lower 2 bits of 695 * the SCSMR register would also need to be set to non-zero values. 696 * 697 * -- Greg Banks 27Feb2000 698 * 699 * Answer: The SCBRR register is only eight bits, and the value in 700 * it gets larger with lower baud rates. At around 2400 (depending on 701 * the peripherial module clock) you run out of bits. However the 702 * lower two bits of SCSMR allow the module clock to be divided down, 703 * scaling the value which is needed in SCBRR. 704 * 705 * -- Stuart Menefy - 23 May 2000 706 * 707 * I meant, why would anyone bother with bitrates below 2400. 708 * 709 * -- Greg Banks - 7Jul2000 710 * 711 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 712 * tape reader as a console! 713 * 714 * -- Mitch Davis - 15 Jul 2000 715 */ 716 717 #if (defined(CONFIG_CPU_SH7780) || \ 718 defined(CONFIG_CPU_SH7785) || \ 719 defined(CONFIG_CPU_SH7786)) && \ 720 !defined(CONFIG_SH_SH2007) 721 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 722 #elif defined(CONFIG_CPU_SH7705) || \ 723 defined(CONFIG_CPU_SH7720) || \ 724 defined(CONFIG_CPU_SH7721) || \ 725 defined(CONFIG_ARCH_SH7367) || \ 726 defined(CONFIG_ARCH_SH7377) || \ 727 defined(CONFIG_ARCH_SH7372) || \ 728 defined(CONFIG_SH73A0) || \ 729 defined(CONFIG_R8A7740) 730 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 731 #elif defined(CONFIG_CPU_SH7723) ||\ 732 defined(CONFIG_CPU_SH7724) 733 static inline int scbrr_calc(struct uart_port *port, int bps, int clk) 734 { 735 if (port->type == PORT_SCIF) 736 return (clk+16*bps)/(32*bps)-1; 737 else 738 return ((clk*2)+16*bps)/(16*bps)-1; 739 } 740 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) 741 #elif defined(__H8300H__) || defined(__H8300S__) 742 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) 743 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 744 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 745 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ 746 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ 747 #else /* Generic SH */ 748 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 749 #endif 750 751 #ifndef DL_VALUE 752 #define DL_VALUE(bps, clk) 0 753 #endif 754