1 /* 2 * Copy and modify from linux/drivers/serial/sh-sci.h 3 */ 4 5 struct uart_port { 6 unsigned long iobase; /* in/out[bwl] */ 7 unsigned char *membase; /* read/write[bwl] */ 8 unsigned long mapbase; /* for ioremap */ 9 unsigned int type; /* port type */ 10 }; 11 12 #define PORT_SCI 52 13 #define PORT_SCIF 53 14 #define PORT_SCIFA 83 15 #define PORT_SCIFB 93 16 17 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 18 #include <asm/regs306x.h> 19 #endif 20 #if defined(CONFIG_H8S2678) 21 #include <asm/regs267x.h> 22 #endif 23 24 #if defined(CONFIG_CPU_SH7706) || \ 25 defined(CONFIG_CPU_SH7707) || \ 26 defined(CONFIG_CPU_SH7708) || \ 27 defined(CONFIG_CPU_SH7709) 28 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 29 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 30 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 31 #elif defined(CONFIG_CPU_SH7705) 32 # define SCIF0 0xA4400000 33 # define SCIF2 0xA4410000 34 # define SCSMR_Ir 0xA44A0000 35 # define IRDA_SCIF SCIF0 36 # define SCPCR 0xA4000116 37 # define SCPDR 0xA4000136 38 39 /* Set the clock source, 40 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 41 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 42 */ 43 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 44 #elif defined(CONFIG_CPU_SH7720) || \ 45 defined(CONFIG_CPU_SH7721) || \ 46 defined(CONFIG_ARCH_SH7367) || \ 47 defined(CONFIG_ARCH_SH7377) || \ 48 defined(CONFIG_ARCH_SH7372) || \ 49 defined(CONFIG_SH73A0) || \ 50 defined(CONFIG_R8A7740) 51 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 52 # define PORT_PTCR 0xA405011EUL 53 # define PORT_PVCR 0xA4050122UL 54 # define SCIF_ORER 0x0200 /* overrun error bit */ 55 #elif defined(CONFIG_SH_RTS7751R2D) 56 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 57 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 58 # define SCIF_ORER 0x0001 /* overrun error bit */ 59 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 60 #elif defined(CONFIG_CPU_SH7750) || \ 61 defined(CONFIG_CPU_SH7750R) || \ 62 defined(CONFIG_CPU_SH7750S) || \ 63 defined(CONFIG_CPU_SH7091) || \ 64 defined(CONFIG_CPU_SH7751) || \ 65 defined(CONFIG_CPU_SH7751R) 66 # define SCSPTR1 0xffe0001c /* 8 bit SCI */ 67 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 68 # define SCIF_ORER 0x0001 /* overrun error bit */ 69 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 70 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 71 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 72 #elif defined(CONFIG_CPU_SH7760) 73 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 74 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 75 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 76 # define SCIF_ORER 0x0001 /* overrun error bit */ 77 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 78 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 79 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 80 # define SCIF_ORER 0x0001 /* overrun error bit */ 81 # define PACR 0xa4050100 82 # define PBCR 0xa4050102 83 # define SCSCR_INIT(port) 0x3B 84 #elif defined(CONFIG_CPU_SH7343) 85 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 86 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 87 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 88 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 89 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 90 #elif defined(CONFIG_CPU_SH7722) 91 # define PADR 0xA4050120 92 # undef PSDR 93 # define PSDR 0xA405013e 94 # define PWDR 0xA4050166 95 # define PSCR 0xA405011E 96 # define SCIF_ORER 0x0001 /* overrun error bit */ 97 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 98 #elif defined(CONFIG_CPU_SH7366) 99 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 100 # define SCSPTR0 SCPDR0 101 # define SCIF_ORER 0x0001 /* overrun error bit */ 102 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 103 #elif defined(CONFIG_CPU_SH7723) 104 # define SCSPTR0 0xa4050160 105 # define SCSPTR1 0xa405013e 106 # define SCSPTR2 0xa4050160 107 # define SCSPTR3 0xa405013e 108 # define SCSPTR4 0xa4050128 109 # define SCSPTR5 0xa4050128 110 # define SCIF_ORER 0x0001 /* overrun error bit */ 111 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 112 #elif defined(CONFIG_CPU_SH7724) 113 # define SCIF_ORER 0x0001 /* overrun error bit */ 114 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 115 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 116 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 117 #elif defined(CONFIG_CPU_SH7734) 118 # define SCSPTR0 0xFFE40020 119 # define SCSPTR1 0xFFE41020 120 # define SCSPTR2 0xFFE42020 121 # define SCSPTR3 0xFFE43020 122 # define SCSPTR4 0xFFE44020 123 # define SCSPTR5 0xFFE45020 124 # define SCIF_ORER 0x0001 /* overrun error bit */ 125 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 126 #elif defined(CONFIG_CPU_SH4_202) 127 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 128 # define SCIF_ORER 0x0001 /* overrun error bit */ 129 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 130 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) 131 # define SCIF_BASE_ADDR 0x01030000 132 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) 133 # define SCIF_PTR2_OFFS 0x0000020 134 # define SCIF_LSR2_OFFS 0x0000024 135 # define SCSPTR\ 136 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 137 # define SCLSR2\ 138 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 139 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 140 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 141 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 142 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 143 #elif defined(CONFIG_H8S2678) 144 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 145 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 146 #elif defined(CONFIG_CPU_SH7757) || \ 147 defined(CONFIG_CPU_SH7752) || \ 148 defined(CONFIG_CPU_SH7753) 149 # define SCSPTR0 0xfe4b0020 150 # define SCSPTR1 0xfe4b0020 151 # define SCSPTR2 0xfe4b0020 152 # define SCIF_ORER 0x0001 153 # define SCSCR_INIT(port) 0x38 154 # define SCIF_ONLY 155 #elif defined(CONFIG_CPU_SH7763) 156 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 157 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 158 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 159 # define SCIF_ORER 0x0001 /* overrun error bit */ 160 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 161 #elif defined(CONFIG_CPU_SH7770) 162 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 163 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 164 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 165 # define SCIF_ORER 0x0001 /* overrun error bit */ 166 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 167 #elif defined(CONFIG_CPU_SH7780) 168 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 169 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 170 # define SCIF_ORER 0x0001 /* Overrun error bit */ 171 172 #if defined(CONFIG_SH_SH2007) 173 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ 174 # define SCSCR_INIT(port) 0x38 175 #else 176 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ 177 # define SCSCR_INIT(port) 0x3a 178 #endif 179 180 #elif defined(CONFIG_CPU_SH7785) || \ 181 defined(CONFIG_CPU_SH7786) 182 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 183 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 184 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 185 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 186 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 187 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 188 # define SCIF_ORER 0x0001 /* Overrun error bit */ 189 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 190 #elif defined(CONFIG_CPU_SH7201) || \ 191 defined(CONFIG_CPU_SH7203) || \ 192 defined(CONFIG_CPU_SH7206) || \ 193 defined(CONFIG_CPU_SH7263) || \ 194 defined(CONFIG_CPU_SH7264) 195 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 196 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 197 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 198 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 199 # if defined(CONFIG_CPU_SH7201) 200 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 201 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 202 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 203 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 204 # endif 205 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 206 #elif defined(CONFIG_CPU_SH7269) 207 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ 208 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ 209 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ 210 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */ 211 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */ 212 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */ 213 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ 214 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ 215 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 216 #elif defined(CONFIG_CPU_SH7619) 217 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 218 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 219 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 220 # define SCIF_ORER 0x0001 /* overrun error bit */ 221 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 222 #elif defined(CONFIG_CPU_SHX3) 223 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 224 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 225 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 226 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 227 # define SCIF_ORER 0x0001 /* Overrun error bit */ 228 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 229 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 230 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 231 # define SCIF_ORER 0x0001 232 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ 233 #else 234 # error CPU subtype not defined 235 #endif 236 237 /* SCSCR */ 238 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 239 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 240 #define SCI_CTRL_FLAGS_TE 0x20 /* all */ 241 #define SCI_CTRL_FLAGS_RE 0x10 /* all */ 242 #if defined(CONFIG_CPU_SH7750) || \ 243 defined(CONFIG_CPU_SH7091) || \ 244 defined(CONFIG_CPU_SH7750R) || \ 245 defined(CONFIG_CPU_SH7722) || \ 246 defined(CONFIG_CPU_SH7734) || \ 247 defined(CONFIG_CPU_SH7750S) || \ 248 defined(CONFIG_CPU_SH7751) || \ 249 defined(CONFIG_CPU_SH7751R) || \ 250 defined(CONFIG_CPU_SH7763) || \ 251 defined(CONFIG_CPU_SH7780) || \ 252 defined(CONFIG_CPU_SH7785) || \ 253 defined(CONFIG_CPU_SH7786) || \ 254 defined(CONFIG_CPU_SHX3) 255 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 256 #elif defined(CONFIG_CPU_SH7724) 257 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) 258 #else 259 #define SCI_CTRL_FLAGS_REIE 0 260 #endif 261 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 262 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 263 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 264 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 265 266 /* SCxSR SCI */ 267 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 268 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 269 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 270 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 271 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 272 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 273 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 274 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 275 276 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 277 278 /* SCxSR SCIF */ 279 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 280 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 281 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 282 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 283 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 284 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 285 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 286 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 287 288 #if defined(CONFIG_CPU_SH7705) || \ 289 defined(CONFIG_CPU_SH7720) || \ 290 defined(CONFIG_CPU_SH7721) || \ 291 defined(CONFIG_ARCH_SH7367) || \ 292 defined(CONFIG_ARCH_SH7377) || \ 293 defined(CONFIG_ARCH_SH7372) || \ 294 defined(CONFIG_SH73A0) || \ 295 defined(CONFIG_R8A7740) 296 # define SCIF_ORER 0x0200 297 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 298 # define SCIF_RFDC_MASK 0x007f 299 # define SCIF_TXROOM_MAX 64 300 #elif defined(CONFIG_CPU_SH7763) 301 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 302 # define SCIF_RFDC_MASK 0x007f 303 # define SCIF_TXROOM_MAX 64 304 /* SH7763 SCIF2 support */ 305 # define SCIF2_RFDC_MASK 0x001f 306 # define SCIF2_TXROOM_MAX 16 307 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 308 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 309 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 310 # define SCIF_RFDC_MASK 0x003f 311 #else 312 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 313 # define SCIF_RFDC_MASK 0x001f 314 # define SCIF_TXROOM_MAX 16 315 #endif 316 317 #ifndef SCIF_ORER 318 #define SCIF_ORER 0x0000 319 #endif 320 321 #define SCxSR_TEND(port)\ 322 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 323 #define SCxSR_ERRORS(port)\ 324 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 325 #define SCxSR_RDxF(port)\ 326 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 327 #define SCxSR_TDxE(port)\ 328 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 329 #define SCxSR_FER(port)\ 330 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 331 #define SCxSR_PER(port)\ 332 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 333 #define SCxSR_BRK(port)\ 334 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 335 #define SCxSR_ORER(port)\ 336 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 337 338 #if defined(CONFIG_CPU_SH7705) || \ 339 defined(CONFIG_CPU_SH7720) || \ 340 defined(CONFIG_CPU_SH7721) || \ 341 defined(CONFIG_ARCH_SH7367) || \ 342 defined(CONFIG_ARCH_SH7377) || \ 343 defined(CONFIG_ARCH_SH7372) || \ 344 defined(CONFIG_SH73A0) || \ 345 defined(CONFIG_R8A7740) 346 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 347 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 348 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 349 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 350 #else 351 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 352 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 353 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 354 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 355 #endif 356 357 /* SCFCR */ 358 #define SCFCR_RFRST 0x0002 359 #define SCFCR_TFRST 0x0004 360 #define SCFCR_TCRST 0x4000 361 #define SCFCR_MCE 0x0008 362 363 #define SCI_MAJOR 204 364 #define SCI_MINOR_START 8 365 366 /* Generic serial flags */ 367 #define SCI_RX_THROTTLE 0x0000001 368 369 #define SCI_MAGIC 0xbabeface 370 371 /* 372 * Events are used to schedule things to happen at timer-interrupt 373 * time, instead of at rs interrupt time. 374 */ 375 #define SCI_EVENT_WRITE_WAKEUP 0 376 377 #define SCI_IN(size, offset)\ 378 if ((size) == 8) {\ 379 return readb(port->membase + (offset));\ 380 } else {\ 381 return readw(port->membase + (offset));\ 382 } 383 #define SCI_OUT(size, offset, value)\ 384 if ((size) == 8) {\ 385 writeb(value, port->membase + (offset));\ 386 } else if ((size) == 16) {\ 387 writew(value, port->membase + (offset));\ 388 } 389 390 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 391 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 392 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 393 SCI_IN(scif_size, scif_offset)\ 394 } else { /* PORT_SCI or PORT_SCIFA */\ 395 SCI_IN(sci_size, sci_offset);\ 396 }\ 397 }\ 398 static inline void sci_##name##_out(struct uart_port *port,\ 399 unsigned int value) {\ 400 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 401 SCI_OUT(scif_size, scif_offset, value)\ 402 } else { /* PORT_SCI or PORT_SCIFA */\ 403 SCI_OUT(sci_size, sci_offset, value);\ 404 }\ 405 } 406 407 #ifdef CONFIG_H8300 408 /* h8300 don't have SCIF */ 409 #define CPU_SCIF_FNS(name) \ 410 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 411 return 0;\ 412 }\ 413 static inline void sci_##name##_out(struct uart_port *port,\ 414 unsigned int value) {\ 415 } 416 #else 417 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 418 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 419 SCI_IN(scif_size, scif_offset);\ 420 }\ 421 static inline void sci_##name##_out(struct uart_port *port,\ 422 unsigned int value) {\ 423 SCI_OUT(scif_size, scif_offset, value);\ 424 } 425 #endif 426 427 #define CPU_SCI_FNS(name, sci_offset, sci_size)\ 428 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 429 SCI_IN(sci_size, sci_offset);\ 430 }\ 431 static inline void sci_##name##_out(struct uart_port *port,\ 432 unsigned int value) {\ 433 SCI_OUT(sci_size, sci_offset, value);\ 434 } 435 436 #if defined(CONFIG_CPU_SH3) || \ 437 defined(CONFIG_ARCH_SH7367) || \ 438 defined(CONFIG_ARCH_SH7377) || \ 439 defined(CONFIG_ARCH_SH7372) || \ 440 defined(CONFIG_SH73A0) || \ 441 defined(CONFIG_R8A7740) 442 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 443 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 444 sh4_sci_offset, sh4_sci_size, \ 445 sh3_scif_offset, sh3_scif_size, \ 446 sh4_scif_offset, sh4_scif_size, \ 447 h8_sci_offset, h8_sci_size) \ 448 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 449 sh4_scif_offset, sh4_scif_size) 450 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 451 sh4_scif_offset, sh4_scif_size) \ 452 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 453 #elif defined(CONFIG_CPU_SH7705) || \ 454 defined(CONFIG_CPU_SH7720) || \ 455 defined(CONFIG_CPU_SH7721) || \ 456 defined(CONFIG_ARCH_SH7367) || \ 457 defined(CONFIG_ARCH_SH7377) || \ 458 defined(CONFIG_SH73A0) 459 #define SCIF_FNS(name, scif_offset, scif_size) \ 460 CPU_SCIF_FNS(name, scif_offset, scif_size) 461 #elif defined(CONFIG_ARCH_SH7372) || \ 462 defined(CONFIG_R8A7740) 463 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 464 sh4_scifb_offset, sh4_scifb_size) \ 465 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 466 sh4_scifb_offset, sh4_scifb_size) 467 #define SCIF_FNS(name, scif_offset, scif_size) \ 468 CPU_SCIF_FNS(name, scif_offset, scif_size) 469 #else 470 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 471 sh4_sci_offset, sh4_sci_size, \ 472 sh3_scif_offset, sh3_scif_size,\ 473 sh4_scif_offset, sh4_scif_size, \ 474 h8_sci_offset, h8_sci_size) \ 475 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 476 sh3_scif_offset, sh3_scif_size) 477 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 478 sh4_scif_offset, sh4_scif_size) \ 479 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 480 #endif 481 #elif defined(__H8300H__) || defined(__H8300S__) 482 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 483 sh4_sci_offset, sh4_sci_size, \ 484 sh3_scif_offset, sh3_scif_size,\ 485 sh4_scif_offset, sh4_scif_size, \ 486 h8_sci_offset, h8_sci_size) \ 487 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 488 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 489 sh4_scif_offset, sh4_scif_size) \ 490 CPU_SCIF_FNS(name) 491 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) 492 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 493 sh4_scif_offset, sh4_scif_size) \ 494 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 495 sh4_scif_offset, sh4_scif_size) 496 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 497 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 498 #else 499 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 500 sh4_sci_offset, sh4_sci_size, \ 501 sh3_scif_offset, sh3_scif_size,\ 502 sh4_scif_offset, sh4_scif_size, \ 503 h8_sci_offset, h8_sci_size) \ 504 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 505 sh4_scif_offset, sh4_scif_size) 506 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ 507 sh4_scif_offset, sh4_scif_size) \ 508 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 509 #endif 510 511 #if defined(CONFIG_CPU_SH7705) || \ 512 defined(CONFIG_CPU_SH7720) || \ 513 defined(CONFIG_CPU_SH7721) || \ 514 defined(CONFIG_ARCH_SH7367) || \ 515 defined(CONFIG_ARCH_SH7377) || \ 516 defined(CONFIG_SH73A0) 517 518 SCIF_FNS(SCSMR, 0x00, 16) 519 SCIF_FNS(SCBRR, 0x04, 8) 520 SCIF_FNS(SCSCR, 0x08, 16) 521 SCIF_FNS(SCTDSR, 0x0c, 8) 522 SCIF_FNS(SCFER, 0x10, 16) 523 SCIF_FNS(SCxSR, 0x14, 16) 524 SCIF_FNS(SCFCR, 0x18, 16) 525 SCIF_FNS(SCFDR, 0x1c, 16) 526 SCIF_FNS(SCxTDR, 0x20, 8) 527 SCIF_FNS(SCxRDR, 0x24, 8) 528 SCIF_FNS(SCLSR, 0x00, 0) 529 #elif defined(CONFIG_ARCH_SH7372) || \ 530 defined(CONFIG_R8A7740) 531 SCIF_FNS(SCSMR, 0x00, 16) 532 SCIF_FNS(SCBRR, 0x04, 8) 533 SCIF_FNS(SCSCR, 0x08, 16) 534 SCIF_FNS(SCTDSR, 0x0c, 16) 535 SCIF_FNS(SCFER, 0x10, 16) 536 SCIF_FNS(SCxSR, 0x14, 16) 537 SCIF_FNS(SCFCR, 0x18, 16) 538 SCIF_FNS(SCFDR, 0x1c, 16) 539 SCIF_FNS(SCTFDR, 0x38, 16) 540 SCIF_FNS(SCRFDR, 0x3c, 16) 541 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 542 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 543 SCIF_FNS(SCLSR, 0x00, 0) 544 #elif defined(CONFIG_CPU_SH7723) ||\ 545 defined(CONFIG_CPU_SH7724) 546 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 547 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 548 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 549 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 550 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 551 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 552 SCIx_FNS(SCSPTR, 0, 0, 0, 0) 553 SCIF_FNS(SCTDSR, 0x0c, 8) 554 SCIF_FNS(SCFER, 0x10, 16) 555 SCIF_FNS(SCFCR, 0x18, 16) 556 SCIF_FNS(SCFDR, 0x1c, 16) 557 SCIF_FNS(SCLSR, 0x24, 16) 558 #else 559 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 560 /* name off sz off sz off sz off sz off sz*/ 561 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 562 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 563 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 564 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 565 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 566 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 567 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 568 #if defined(CONFIG_CPU_SH7760) || \ 569 defined(CONFIG_CPU_SH7780) || \ 570 defined(CONFIG_CPU_SH7785) || \ 571 defined(CONFIG_CPU_SH7786) 572 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 573 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 574 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 575 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 576 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 577 #elif defined(CONFIG_CPU_SH7763) 578 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 579 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 580 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) 581 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 582 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 583 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 584 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 585 #else 586 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 587 #if defined(CONFIG_CPU_SH7722) 588 SCIF_FNS(SCSPTR, 0, 0, 0, 0) 589 #else 590 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 591 #endif 592 #if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 593 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 594 SCIF_FNS(DL, 0, 0, 0x30, 16) 595 SCIF_FNS(CKS, 0, 0, 0x34, 16) 596 #endif 597 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 598 #endif 599 #endif 600 #define sci_in(port, reg) sci_##reg##_in(port) 601 #define sci_out(port, reg, value) sci_##reg##_out(port, value) 602 603 /* H8/300 series SCI pins assignment */ 604 #if defined(__H8300H__) || defined(__H8300S__) 605 static const struct __attribute__((packed)) { 606 int port; /* GPIO port no */ 607 unsigned short rx, tx; /* GPIO bit no */ 608 } h8300_sci_pins[] = { 609 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 610 { /* SCI0 */ 611 .port = H8300_GPIO_P9, 612 .rx = H8300_GPIO_B2, 613 .tx = H8300_GPIO_B0, 614 }, 615 { /* SCI1 */ 616 .port = H8300_GPIO_P9, 617 .rx = H8300_GPIO_B3, 618 .tx = H8300_GPIO_B1, 619 }, 620 { /* SCI2 */ 621 .port = H8300_GPIO_PB, 622 .rx = H8300_GPIO_B7, 623 .tx = H8300_GPIO_B6, 624 } 625 #elif defined(CONFIG_H8S2678) 626 { /* SCI0 */ 627 .port = H8300_GPIO_P3, 628 .rx = H8300_GPIO_B2, 629 .tx = H8300_GPIO_B0, 630 }, 631 { /* SCI1 */ 632 .port = H8300_GPIO_P3, 633 .rx = H8300_GPIO_B3, 634 .tx = H8300_GPIO_B1, 635 }, 636 { /* SCI2 */ 637 .port = H8300_GPIO_P5, 638 .rx = H8300_GPIO_B1, 639 .tx = H8300_GPIO_B0, 640 } 641 #endif 642 }; 643 #endif 644 645 #if defined(CONFIG_CPU_SH7706) || \ 646 defined(CONFIG_CPU_SH7707) || \ 647 defined(CONFIG_CPU_SH7708) || \ 648 defined(CONFIG_CPU_SH7709) 649 static inline int sci_rxd_in(struct uart_port *port) 650 { 651 if (port->mapbase == 0xfffffe80) 652 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 653 return 1; 654 } 655 #elif defined(CONFIG_CPU_SH7750) || \ 656 defined(CONFIG_CPU_SH7751) || \ 657 defined(CONFIG_CPU_SH7751R) || \ 658 defined(CONFIG_CPU_SH7750R) || \ 659 defined(CONFIG_CPU_SH7750S) || \ 660 defined(CONFIG_CPU_SH7091) 661 static inline int sci_rxd_in(struct uart_port *port) 662 { 663 if (port->mapbase == 0xffe00000) 664 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 665 return 1; 666 } 667 #elif defined(__H8300H__) || defined(__H8300S__) 668 static inline int sci_rxd_in(struct uart_port *port) 669 { 670 int ch = (port->mapbase - SMR0) >> 3; 671 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 672 } 673 #else /* default case for non-SCI processors */ 674 static inline int sci_rxd_in(struct uart_port *port) 675 { 676 return 1; 677 } 678 #endif 679 680 /* 681 * Values for the BitRate Register (SCBRR) 682 * 683 * The values are actually divisors for a frequency which can 684 * be internal to the SH3 (14.7456MHz) or derived from an external 685 * clock source. This driver assumes the internal clock is used; 686 * to support using an external clock source, config options or 687 * possibly command-line options would need to be added. 688 * 689 * Also, to support speeds below 2400 (why?) the lower 2 bits of 690 * the SCSMR register would also need to be set to non-zero values. 691 * 692 * -- Greg Banks 27Feb2000 693 * 694 * Answer: The SCBRR register is only eight bits, and the value in 695 * it gets larger with lower baud rates. At around 2400 (depending on 696 * the peripherial module clock) you run out of bits. However the 697 * lower two bits of SCSMR allow the module clock to be divided down, 698 * scaling the value which is needed in SCBRR. 699 * 700 * -- Stuart Menefy - 23 May 2000 701 * 702 * I meant, why would anyone bother with bitrates below 2400. 703 * 704 * -- Greg Banks - 7Jul2000 705 * 706 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 707 * tape reader as a console! 708 * 709 * -- Mitch Davis - 15 Jul 2000 710 */ 711 712 #if (defined(CONFIG_CPU_SH7780) || \ 713 defined(CONFIG_CPU_SH7785) || \ 714 defined(CONFIG_CPU_SH7786)) && \ 715 !defined(CONFIG_SH_SH2007) 716 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 717 #elif defined(CONFIG_CPU_SH7705) || \ 718 defined(CONFIG_CPU_SH7720) || \ 719 defined(CONFIG_CPU_SH7721) || \ 720 defined(CONFIG_ARCH_SH7367) || \ 721 defined(CONFIG_ARCH_SH7377) || \ 722 defined(CONFIG_ARCH_SH7372) || \ 723 defined(CONFIG_SH73A0) || \ 724 defined(CONFIG_R8A7740) 725 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 726 #elif defined(CONFIG_CPU_SH7723) ||\ 727 defined(CONFIG_CPU_SH7724) 728 static inline int scbrr_calc(struct uart_port port, int bps, int clk) 729 { 730 if (port.type == PORT_SCIF) 731 return (clk+16*bps)/(32*bps)-1; 732 else 733 return ((clk*2)+16*bps)/(16*bps)-1; 734 } 735 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) 736 #elif defined(__H8300H__) || defined(__H8300S__) 737 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) 738 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 739 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 740 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ 741 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ 742 #else /* Generic SH */ 743 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 744 #endif 745