1 /* 2 * Copy and modify from linux/drivers/serial/sh-sci.h 3 */ 4 5 struct uart_port { 6 unsigned long iobase; /* in/out[bwl] */ 7 unsigned char *membase; /* read/write[bwl] */ 8 unsigned long mapbase; /* for ioremap */ 9 unsigned int type; /* port type */ 10 }; 11 12 #define PORT_SCI 52 13 #define PORT_SCIF 53 14 #define PORT_SCIFA 83 15 #define PORT_SCIFB 93 16 17 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 18 #include <asm/regs306x.h> 19 #endif 20 #if defined(CONFIG_H8S2678) 21 #include <asm/regs267x.h> 22 #endif 23 24 #if defined(CONFIG_CPU_SH7706) || \ 25 defined(CONFIG_CPU_SH7707) || \ 26 defined(CONFIG_CPU_SH7708) || \ 27 defined(CONFIG_CPU_SH7709) 28 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 29 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 30 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 31 #elif defined(CONFIG_CPU_SH7705) 32 # define SCIF0 0xA4400000 33 # define SCIF2 0xA4410000 34 # define SCSMR_Ir 0xA44A0000 35 # define IRDA_SCIF SCIF0 36 # define SCPCR 0xA4000116 37 # define SCPDR 0xA4000136 38 39 /* Set the clock source, 40 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 41 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 42 */ 43 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 44 #elif defined(CONFIG_CPU_SH7720) || \ 45 defined(CONFIG_CPU_SH7721) || \ 46 defined(CONFIG_ARCH_SH7367) || \ 47 defined(CONFIG_ARCH_SH7377) || \ 48 defined(CONFIG_ARCH_SH7372) 49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 50 # define PORT_PTCR 0xA405011EUL 51 # define PORT_PVCR 0xA4050122UL 52 # define SCIF_ORER 0x0200 /* overrun error bit */ 53 #elif defined(CONFIG_SH_RTS7751R2D) 54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 56 # define SCIF_ORER 0x0001 /* overrun error bit */ 57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 58 #elif defined(CONFIG_CPU_SH7750) || \ 59 defined(CONFIG_CPU_SH7750R) || \ 60 defined(CONFIG_CPU_SH7750S) || \ 61 defined(CONFIG_CPU_SH7091) || \ 62 defined(CONFIG_CPU_SH7751) || \ 63 defined(CONFIG_CPU_SH7751R) 64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */ 65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 66 # define SCIF_ORER 0x0001 /* overrun error bit */ 67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 70 #elif defined(CONFIG_CPU_SH7760) 71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 74 # define SCIF_ORER 0x0001 /* overrun error bit */ 75 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 77 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 78 # define SCIF_ORER 0x0001 /* overrun error bit */ 79 # define PACR 0xa4050100 80 # define PBCR 0xa4050102 81 # define SCSCR_INIT(port) 0x3B 82 #elif defined(CONFIG_CPU_SH7343) 83 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 84 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 85 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 86 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 87 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 88 #elif defined(CONFIG_CPU_SH7722) 89 # define PADR 0xA4050120 90 # undef PSDR 91 # define PSDR 0xA405013e 92 # define PWDR 0xA4050166 93 # define PSCR 0xA405011E 94 # define SCIF_ORER 0x0001 /* overrun error bit */ 95 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 96 #elif defined(CONFIG_CPU_SH7366) 97 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 98 # define SCSPTR0 SCPDR0 99 # define SCIF_ORER 0x0001 /* overrun error bit */ 100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 101 #elif defined(CONFIG_CPU_SH7723) 102 # define SCSPTR0 0xa4050160 103 # define SCSPTR1 0xa405013e 104 # define SCSPTR2 0xa4050160 105 # define SCSPTR3 0xa405013e 106 # define SCSPTR4 0xa4050128 107 # define SCSPTR5 0xa4050128 108 # define SCIF_ORER 0x0001 /* overrun error bit */ 109 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 110 #elif defined(CONFIG_CPU_SH7724) 111 # define SCIF_ORER 0x0001 /* overrun error bit */ 112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 115 #elif defined(CONFIG_CPU_SH7734) 116 # define SCSPTR0 0xFFE40020 117 # define SCSPTR1 0xFFE41020 118 # define SCSPTR2 0xFFE42020 119 # define SCSPTR3 0xFFE43020 120 # define SCSPTR4 0xFFE44020 121 # define SCSPTR5 0xFFE45020 122 # define SCIF_ORER 0x0001 /* overrun error bit */ 123 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 124 #elif defined(CONFIG_CPU_SH4_202) 125 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 126 # define SCIF_ORER 0x0001 /* overrun error bit */ 127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 128 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) 129 # define SCIF_BASE_ADDR 0x01030000 130 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) 131 # define SCIF_PTR2_OFFS 0x0000020 132 # define SCIF_LSR2_OFFS 0x0000024 133 # define SCSPTR\ 134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 135 # define SCLSR2\ 136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 137 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 138 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 139 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 140 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 141 #elif defined(CONFIG_H8S2678) 142 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 143 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 144 #elif defined(CONFIG_CPU_SH7757) 145 # define SCSPTR0 0xfe4b0020 146 # define SCSPTR1 0xfe4b0020 147 # define SCSPTR2 0xfe4b0020 148 # define SCIF_ORER 0x0001 149 # define SCSCR_INIT(port) 0x38 150 # define SCIF_ONLY 151 #elif defined(CONFIG_CPU_SH7763) 152 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 153 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 154 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 155 # define SCIF_ORER 0x0001 /* overrun error bit */ 156 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 157 #elif defined(CONFIG_CPU_SH7770) 158 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 159 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 160 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 161 # define SCIF_ORER 0x0001 /* overrun error bit */ 162 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 163 #elif defined(CONFIG_CPU_SH7780) 164 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 165 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 166 # define SCIF_ORER 0x0001 /* Overrun error bit */ 167 168 #if defined(CONFIG_SH_SH2007) 169 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ 170 # define SCSCR_INIT(port) 0x38 171 #else 172 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ 173 # define SCSCR_INIT(port) 0x3a 174 #endif 175 176 #elif defined(CONFIG_CPU_SH7785) || \ 177 defined(CONFIG_CPU_SH7786) 178 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 179 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 180 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 181 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 182 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 183 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 184 # define SCIF_ORER 0x0001 /* Overrun error bit */ 185 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 186 #elif defined(CONFIG_CPU_SH7201) || \ 187 defined(CONFIG_CPU_SH7203) || \ 188 defined(CONFIG_CPU_SH7206) || \ 189 defined(CONFIG_CPU_SH7263) || \ 190 defined(CONFIG_CPU_SH7264) 191 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 192 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 193 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 194 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 195 # if defined(CONFIG_CPU_SH7201) 196 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 197 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 198 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 199 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 200 # endif 201 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 202 #elif defined(CONFIG_CPU_SH7269) 203 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ 204 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ 205 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ 206 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */ 207 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */ 208 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */ 209 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ 210 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ 211 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 212 #elif defined(CONFIG_CPU_SH7619) 213 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 214 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 215 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 216 # define SCIF_ORER 0x0001 /* overrun error bit */ 217 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 218 #elif defined(CONFIG_CPU_SHX3) 219 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 220 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 221 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 222 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 223 # define SCIF_ORER 0x0001 /* Overrun error bit */ 224 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 225 #else 226 # error CPU subtype not defined 227 #endif 228 229 /* SCSCR */ 230 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 231 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 232 #define SCI_CTRL_FLAGS_TE 0x20 /* all */ 233 #define SCI_CTRL_FLAGS_RE 0x10 /* all */ 234 #if defined(CONFIG_CPU_SH7750) || \ 235 defined(CONFIG_CPU_SH7091) || \ 236 defined(CONFIG_CPU_SH7750R) || \ 237 defined(CONFIG_CPU_SH7722) || \ 238 defined(CONFIG_CPU_SH7734) || \ 239 defined(CONFIG_CPU_SH7750S) || \ 240 defined(CONFIG_CPU_SH7751) || \ 241 defined(CONFIG_CPU_SH7751R) || \ 242 defined(CONFIG_CPU_SH7763) || \ 243 defined(CONFIG_CPU_SH7780) || \ 244 defined(CONFIG_CPU_SH7785) || \ 245 defined(CONFIG_CPU_SH7786) || \ 246 defined(CONFIG_CPU_SHX3) 247 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 248 #elif defined(CONFIG_CPU_SH7724) 249 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) 250 #else 251 #define SCI_CTRL_FLAGS_REIE 0 252 #endif 253 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 254 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 255 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 256 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 257 258 /* SCxSR SCI */ 259 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 260 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 261 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 262 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 263 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 264 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 265 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 266 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 267 268 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 269 270 /* SCxSR SCIF */ 271 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 272 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 273 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 274 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 275 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 276 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 277 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 278 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 279 280 #if defined(CONFIG_CPU_SH7705) || \ 281 defined(CONFIG_CPU_SH7720) || \ 282 defined(CONFIG_CPU_SH7721) || \ 283 defined(CONFIG_ARCH_SH7367) || \ 284 defined(CONFIG_ARCH_SH7377) || \ 285 defined(CONFIG_ARCH_SH7372) 286 # define SCIF_ORER 0x0200 287 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 288 # define SCIF_RFDC_MASK 0x007f 289 # define SCIF_TXROOM_MAX 64 290 #elif defined(CONFIG_CPU_SH7763) 291 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 292 # define SCIF_RFDC_MASK 0x007f 293 # define SCIF_TXROOM_MAX 64 294 /* SH7763 SCIF2 support */ 295 # define SCIF2_RFDC_MASK 0x001f 296 # define SCIF2_TXROOM_MAX 16 297 #else 298 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 299 # define SCIF_RFDC_MASK 0x001f 300 # define SCIF_TXROOM_MAX 16 301 #endif 302 303 #ifndef SCIF_ORER 304 #define SCIF_ORER 0x0000 305 #endif 306 307 #define SCxSR_TEND(port)\ 308 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 309 #define SCxSR_ERRORS(port)\ 310 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 311 #define SCxSR_RDxF(port)\ 312 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 313 #define SCxSR_TDxE(port)\ 314 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 315 #define SCxSR_FER(port)\ 316 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 317 #define SCxSR_PER(port)\ 318 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 319 #define SCxSR_BRK(port)\ 320 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 321 #define SCxSR_ORER(port)\ 322 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 323 324 #if defined(CONFIG_CPU_SH7705) || \ 325 defined(CONFIG_CPU_SH7720) || \ 326 defined(CONFIG_CPU_SH7721) || \ 327 defined(CONFIG_ARCH_SH7367) || \ 328 defined(CONFIG_ARCH_SH7377) || \ 329 defined(CONFIG_ARCH_SH7372) 330 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 331 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 332 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 333 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 334 #else 335 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 336 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 337 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 338 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 339 #endif 340 341 /* SCFCR */ 342 #define SCFCR_RFRST 0x0002 343 #define SCFCR_TFRST 0x0004 344 #define SCFCR_TCRST 0x4000 345 #define SCFCR_MCE 0x0008 346 347 #define SCI_MAJOR 204 348 #define SCI_MINOR_START 8 349 350 /* Generic serial flags */ 351 #define SCI_RX_THROTTLE 0x0000001 352 353 #define SCI_MAGIC 0xbabeface 354 355 /* 356 * Events are used to schedule things to happen at timer-interrupt 357 * time, instead of at rs interrupt time. 358 */ 359 #define SCI_EVENT_WRITE_WAKEUP 0 360 361 #define SCI_IN(size, offset)\ 362 if ((size) == 8) {\ 363 return readb(port->membase + (offset));\ 364 } else {\ 365 return readw(port->membase + (offset));\ 366 } 367 #define SCI_OUT(size, offset, value)\ 368 if ((size) == 8) {\ 369 writeb(value, port->membase + (offset));\ 370 } else if ((size) == 16) {\ 371 writew(value, port->membase + (offset));\ 372 } 373 374 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 375 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 376 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 377 SCI_IN(scif_size, scif_offset)\ 378 } else { /* PORT_SCI or PORT_SCIFA */\ 379 SCI_IN(sci_size, sci_offset);\ 380 }\ 381 }\ 382 static inline void sci_##name##_out(struct uart_port *port,\ 383 unsigned int value) {\ 384 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 385 SCI_OUT(scif_size, scif_offset, value)\ 386 } else { /* PORT_SCI or PORT_SCIFA */\ 387 SCI_OUT(sci_size, sci_offset, value);\ 388 }\ 389 } 390 391 #ifdef CONFIG_H8300 392 /* h8300 don't have SCIF */ 393 #define CPU_SCIF_FNS(name) \ 394 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 395 return 0;\ 396 }\ 397 static inline void sci_##name##_out(struct uart_port *port,\ 398 unsigned int value) {\ 399 } 400 #else 401 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 402 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 403 SCI_IN(scif_size, scif_offset);\ 404 }\ 405 static inline void sci_##name##_out(struct uart_port *port,\ 406 unsigned int value) {\ 407 SCI_OUT(scif_size, scif_offset, value);\ 408 } 409 #endif 410 411 #define CPU_SCI_FNS(name, sci_offset, sci_size)\ 412 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 413 SCI_IN(sci_size, sci_offset);\ 414 }\ 415 static inline void sci_##name##_out(struct uart_port *port,\ 416 unsigned int value) {\ 417 SCI_OUT(sci_size, sci_offset, value);\ 418 } 419 420 #if defined(CONFIG_SH3) || \ 421 defined(CONFIG_ARCH_SH7367) || \ 422 defined(CONFIG_ARCH_SH7377) || \ 423 defined(CONFIG_ARCH_SH7372) 424 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 425 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 426 sh4_sci_offset, sh4_sci_size, \ 427 sh3_scif_offset, sh3_scif_size, \ 428 sh4_scif_offset, sh4_scif_size, \ 429 h8_sci_offset, h8_sci_size) \ 430 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 431 sh4_scif_offset, sh4_scif_size) 432 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 433 sh4_scif_offset, sh4_scif_size) \ 434 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 435 #elif defined(CONFIG_CPU_SH7705) || \ 436 defined(CONFIG_CPU_SH7720) || \ 437 defined(CONFIG_CPU_SH7721) || \ 438 defined(CONFIG_ARCH_SH7367) || \ 439 defined(CONFIG_ARCH_SH7377) 440 #define SCIF_FNS(name, scif_offset, scif_size) \ 441 CPU_SCIF_FNS(name, scif_offset, scif_size) 442 #elif defined(CONFIG_ARCH_SH7372) 443 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 444 sh4_scifb_offset, sh4_scifb_size) \ 445 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 446 sh4_scifb_offset, sh4_scifb_size) 447 #define SCIF_FNS(name, scif_offset, scif_size) \ 448 CPU_SCIF_FNS(name, scif_offset, scif_size) 449 #else 450 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 451 sh4_sci_offset, sh4_sci_size, \ 452 sh3_scif_offset, sh3_scif_size,\ 453 sh4_scif_offset, sh4_scif_size, \ 454 h8_sci_offset, h8_sci_size) \ 455 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 456 sh3_scif_offset, sh3_scif_size) 457 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 458 sh4_scif_offset, sh4_scif_size) \ 459 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 460 #endif 461 #elif defined(__H8300H__) || defined(__H8300S__) 462 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 463 sh4_sci_offset, sh4_sci_size, \ 464 sh3_scif_offset, sh3_scif_size,\ 465 sh4_scif_offset, sh4_scif_size, \ 466 h8_sci_offset, h8_sci_size) \ 467 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 468 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 469 sh4_scif_offset, sh4_scif_size) \ 470 CPU_SCIF_FNS(name) 471 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) 472 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 473 sh4_scif_offset, sh4_scif_size) \ 474 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 475 sh4_scif_offset, sh4_scif_size) 476 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 477 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 478 #else 479 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 480 sh4_sci_offset, sh4_sci_size, \ 481 sh3_scif_offset, sh3_scif_size,\ 482 sh4_scif_offset, sh4_scif_size, \ 483 h8_sci_offset, h8_sci_size) \ 484 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 485 sh4_scif_offset, sh4_scif_size) 486 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ 487 sh4_scif_offset, sh4_scif_size) \ 488 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 489 #endif 490 491 #if defined(CONFIG_CPU_SH7705) || \ 492 defined(CONFIG_CPU_SH7720) || \ 493 defined(CONFIG_CPU_SH7721) || \ 494 defined(CONFIG_ARCH_SH7367) || \ 495 defined(CONFIG_ARCH_SH7377) 496 497 SCIF_FNS(SCSMR, 0x00, 16) 498 SCIF_FNS(SCBRR, 0x04, 8) 499 SCIF_FNS(SCSCR, 0x08, 16) 500 SCIF_FNS(SCTDSR, 0x0c, 8) 501 SCIF_FNS(SCFER, 0x10, 16) 502 SCIF_FNS(SCxSR, 0x14, 16) 503 SCIF_FNS(SCFCR, 0x18, 16) 504 SCIF_FNS(SCFDR, 0x1c, 16) 505 SCIF_FNS(SCxTDR, 0x20, 8) 506 SCIF_FNS(SCxRDR, 0x24, 8) 507 SCIF_FNS(SCLSR, 0x00, 0) 508 #elif defined(CONFIG_ARCH_SH7372) 509 SCIF_FNS(SCSMR, 0x00, 16) 510 SCIF_FNS(SCBRR, 0x04, 8) 511 SCIF_FNS(SCSCR, 0x08, 16) 512 SCIF_FNS(SCTDSR, 0x0c, 16) 513 SCIF_FNS(SCFER, 0x10, 16) 514 SCIF_FNS(SCxSR, 0x14, 16) 515 SCIF_FNS(SCFCR, 0x18, 16) 516 SCIF_FNS(SCFDR, 0x1c, 16) 517 SCIF_FNS(SCTFDR, 0x38, 16) 518 SCIF_FNS(SCRFDR, 0x3c, 16) 519 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 520 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 521 SCIF_FNS(SCLSR, 0x00, 0) 522 #elif defined(CONFIG_CPU_SH7723) ||\ 523 defined(CONFIG_CPU_SH7724) 524 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 525 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 526 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 527 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 528 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 529 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 530 SCIx_FNS(SCSPTR, 0, 0, 0, 0) 531 SCIF_FNS(SCTDSR, 0x0c, 8) 532 SCIF_FNS(SCFER, 0x10, 16) 533 SCIF_FNS(SCFCR, 0x18, 16) 534 SCIF_FNS(SCFDR, 0x1c, 16) 535 SCIF_FNS(SCLSR, 0x24, 16) 536 #else 537 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 538 /* name off sz off sz off sz off sz off sz*/ 539 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 540 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 541 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 542 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 543 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 544 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 545 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 546 #if defined(CONFIG_CPU_SH7760) || \ 547 defined(CONFIG_CPU_SH7780) || \ 548 defined(CONFIG_CPU_SH7785) || \ 549 defined(CONFIG_CPU_SH7786) 550 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 551 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 552 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 553 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 554 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 555 #elif defined(CONFIG_CPU_SH7763) 556 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 557 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 558 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) 559 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 560 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 561 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 562 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 563 #else 564 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 565 #if defined(CONFIG_CPU_SH7722) 566 SCIF_FNS(SCSPTR, 0, 0, 0, 0) 567 #else 568 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 569 #endif 570 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 571 #endif 572 #endif 573 #define sci_in(port, reg) sci_##reg##_in(port) 574 #define sci_out(port, reg, value) sci_##reg##_out(port, value) 575 576 /* H8/300 series SCI pins assignment */ 577 #if defined(__H8300H__) || defined(__H8300S__) 578 static const struct __attribute__((packed)) { 579 int port; /* GPIO port no */ 580 unsigned short rx, tx; /* GPIO bit no */ 581 } h8300_sci_pins[] = { 582 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 583 { /* SCI0 */ 584 .port = H8300_GPIO_P9, 585 .rx = H8300_GPIO_B2, 586 .tx = H8300_GPIO_B0, 587 }, 588 { /* SCI1 */ 589 .port = H8300_GPIO_P9, 590 .rx = H8300_GPIO_B3, 591 .tx = H8300_GPIO_B1, 592 }, 593 { /* SCI2 */ 594 .port = H8300_GPIO_PB, 595 .rx = H8300_GPIO_B7, 596 .tx = H8300_GPIO_B6, 597 } 598 #elif defined(CONFIG_H8S2678) 599 { /* SCI0 */ 600 .port = H8300_GPIO_P3, 601 .rx = H8300_GPIO_B2, 602 .tx = H8300_GPIO_B0, 603 }, 604 { /* SCI1 */ 605 .port = H8300_GPIO_P3, 606 .rx = H8300_GPIO_B3, 607 .tx = H8300_GPIO_B1, 608 }, 609 { /* SCI2 */ 610 .port = H8300_GPIO_P5, 611 .rx = H8300_GPIO_B1, 612 .tx = H8300_GPIO_B0, 613 } 614 #endif 615 }; 616 #endif 617 618 #if defined(CONFIG_CPU_SH7706) || \ 619 defined(CONFIG_CPU_SH7707) || \ 620 defined(CONFIG_CPU_SH7708) || \ 621 defined(CONFIG_CPU_SH7709) 622 static inline int sci_rxd_in(struct uart_port *port) 623 { 624 if (port->mapbase == 0xfffffe80) 625 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 626 return 1; 627 } 628 #elif defined(CONFIG_CPU_SH7750) || \ 629 defined(CONFIG_CPU_SH7751) || \ 630 defined(CONFIG_CPU_SH7751R) || \ 631 defined(CONFIG_CPU_SH7750R) || \ 632 defined(CONFIG_CPU_SH7750S) || \ 633 defined(CONFIG_CPU_SH7091) 634 static inline int sci_rxd_in(struct uart_port *port) 635 { 636 if (port->mapbase == 0xffe00000) 637 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 638 return 1; 639 } 640 #elif defined(__H8300H__) || defined(__H8300S__) 641 static inline int sci_rxd_in(struct uart_port *port) 642 { 643 int ch = (port->mapbase - SMR0) >> 3; 644 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 645 } 646 #else /* default case for non-SCI processors */ 647 static inline int sci_rxd_in(struct uart_port *port) 648 { 649 return 1; 650 } 651 #endif 652 653 /* 654 * Values for the BitRate Register (SCBRR) 655 * 656 * The values are actually divisors for a frequency which can 657 * be internal to the SH3 (14.7456MHz) or derived from an external 658 * clock source. This driver assumes the internal clock is used; 659 * to support using an external clock source, config options or 660 * possibly command-line options would need to be added. 661 * 662 * Also, to support speeds below 2400 (why?) the lower 2 bits of 663 * the SCSMR register would also need to be set to non-zero values. 664 * 665 * -- Greg Banks 27Feb2000 666 * 667 * Answer: The SCBRR register is only eight bits, and the value in 668 * it gets larger with lower baud rates. At around 2400 (depending on 669 * the peripherial module clock) you run out of bits. However the 670 * lower two bits of SCSMR allow the module clock to be divided down, 671 * scaling the value which is needed in SCBRR. 672 * 673 * -- Stuart Menefy - 23 May 2000 674 * 675 * I meant, why would anyone bother with bitrates below 2400. 676 * 677 * -- Greg Banks - 7Jul2000 678 * 679 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 680 * tape reader as a console! 681 * 682 * -- Mitch Davis - 15 Jul 2000 683 */ 684 685 #if (defined(CONFIG_CPU_SH7780) || \ 686 defined(CONFIG_CPU_SH7785) || \ 687 defined(CONFIG_CPU_SH7786)) && \ 688 !defined(CONFIG_SH_SH2007) 689 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 690 #elif defined(CONFIG_CPU_SH7705) || \ 691 defined(CONFIG_CPU_SH7720) || \ 692 defined(CONFIG_CPU_SH7721) || \ 693 defined(CONFIG_ARCH_SH7367) || \ 694 defined(CONFIG_ARCH_SH7377) || \ 695 defined(CONFIG_ARCH_SH7372) 696 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 697 #elif defined(CONFIG_CPU_SH7723) ||\ 698 defined(CONFIG_CPU_SH7724) 699 static inline int scbrr_calc(struct uart_port port, int bps, int clk) 700 { 701 if (port.type == PORT_SCIF) 702 return (clk+16*bps)/(32*bps)-1; 703 else 704 return ((clk*2)+16*bps)/(16*bps)-1; 705 } 706 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) 707 #elif defined(__H8300H__) || defined(__H8300S__) 708 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) 709 #else /* Generic SH */ 710 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 711 #endif 712