1 /* 2 * Copy and modify from linux/drivers/serial/sh-sci.h 3 */ 4 5 #include <dm/platform_data/serial_sh.h> 6 7 struct uart_port { 8 unsigned long iobase; /* in/out[bwl] */ 9 unsigned char *membase; /* read/write[bwl] */ 10 unsigned long mapbase; /* for ioremap */ 11 enum sh_serial_type type; /* port type */ 12 enum sh_clk_mode clk_mode; /* clock mode */ 13 }; 14 15 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 16 #include <asm/regs306x.h> 17 #endif 18 #if defined(CONFIG_H8S2678) 19 #include <asm/regs267x.h> 20 #endif 21 22 #if defined(CONFIG_CPU_SH7706) || \ 23 defined(CONFIG_CPU_SH7707) || \ 24 defined(CONFIG_CPU_SH7708) || \ 25 defined(CONFIG_CPU_SH7709) 26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 27 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 28 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 29 #elif defined(CONFIG_CPU_SH7705) 30 # define SCIF0 0xA4400000 31 # define SCIF2 0xA4410000 32 # define SCSMR_Ir 0xA44A0000 33 # define IRDA_SCIF SCIF0 34 # define SCPCR 0xA4000116 35 # define SCPDR 0xA4000136 36 37 /* Set the clock source, 38 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 39 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 40 */ 41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 42 #elif defined(CONFIG_CPU_SH7720) || \ 43 defined(CONFIG_CPU_SH7721) || \ 44 defined(CONFIG_ARCH_SH7367) || \ 45 defined(CONFIG_ARCH_SH7377) || \ 46 defined(CONFIG_ARCH_SH7372) || \ 47 defined(CONFIG_SH73A0) || \ 48 defined(CONFIG_R8A7740) 49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 50 # define PORT_PTCR 0xA405011EUL 51 # define PORT_PVCR 0xA4050122UL 52 # define SCIF_ORER 0x0200 /* overrun error bit */ 53 #elif defined(CONFIG_SH_RTS7751R2D) 54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 56 # define SCIF_ORER 0x0001 /* overrun error bit */ 57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 58 #elif defined(CONFIG_CPU_SH7750) || \ 59 defined(CONFIG_CPU_SH7750R) || \ 60 defined(CONFIG_CPU_SH7750S) || \ 61 defined(CONFIG_CPU_SH7091) || \ 62 defined(CONFIG_CPU_SH7751) || \ 63 defined(CONFIG_CPU_SH7751R) 64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */ 65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 66 # define SCIF_ORER 0x0001 /* overrun error bit */ 67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 70 #elif defined(CONFIG_CPU_SH7760) 71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 74 # define SCIF_ORER 0x0001 /* overrun error bit */ 75 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 77 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 78 # define SCIF_ORER 0x0001 /* overrun error bit */ 79 # define PACR 0xa4050100 80 # define PBCR 0xa4050102 81 # define SCSCR_INIT(port) 0x3B 82 #elif defined(CONFIG_CPU_SH7343) 83 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 84 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 85 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 86 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 87 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 88 #elif defined(CONFIG_CPU_SH7722) 89 # define PADR 0xA4050120 90 # undef PSDR 91 # define PSDR 0xA405013e 92 # define PWDR 0xA4050166 93 # define PSCR 0xA405011E 94 # define SCIF_ORER 0x0001 /* overrun error bit */ 95 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 96 #elif defined(CONFIG_CPU_SH7366) 97 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 98 # define SCSPTR0 SCPDR0 99 # define SCIF_ORER 0x0001 /* overrun error bit */ 100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 101 #elif defined(CONFIG_CPU_SH7723) 102 # define SCSPTR0 0xa4050160 103 # define SCSPTR1 0xa405013e 104 # define SCSPTR2 0xa4050160 105 # define SCSPTR3 0xa405013e 106 # define SCSPTR4 0xa4050128 107 # define SCSPTR5 0xa4050128 108 # define SCIF_ORER 0x0001 /* overrun error bit */ 109 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 110 #elif defined(CONFIG_CPU_SH7724) 111 # define SCIF_ORER 0x0001 /* overrun error bit */ 112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) 115 #elif defined(CONFIG_CPU_SH7734) 116 # define SCSPTR0 0xFFE40020 117 # define SCSPTR1 0xFFE41020 118 # define SCSPTR2 0xFFE42020 119 # define SCSPTR3 0xFFE43020 120 # define SCSPTR4 0xFFE44020 121 # define SCSPTR5 0xFFE45020 122 # define SCIF_ORER 0x0001 /* overrun error bit */ 123 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 124 #elif defined(CONFIG_CPU_SH4_202) 125 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 126 # define SCIF_ORER 0x0001 /* overrun error bit */ 127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 128 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) 129 # define SCIF_BASE_ADDR 0x01030000 130 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) 131 # define SCIF_PTR2_OFFS 0x0000020 132 # define SCIF_LSR2_OFFS 0x0000024 133 # define SCSPTR\ 134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 135 # define SCLSR2\ 136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 137 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 138 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 139 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 140 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 141 #elif defined(CONFIG_H8S2678) 142 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 143 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) 144 #elif defined(CONFIG_CPU_SH7757) || \ 145 defined(CONFIG_CPU_SH7752) || \ 146 defined(CONFIG_CPU_SH7753) 147 # define SCSPTR0 0xfe4b0020 148 # define SCSPTR1 0xfe4b0020 149 # define SCSPTR2 0xfe4b0020 150 # define SCIF_ORER 0x0001 151 # define SCSCR_INIT(port) 0x38 152 # define SCIF_ONLY 153 #elif defined(CONFIG_CPU_SH7763) 154 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 155 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 156 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 157 # define SCIF_ORER 0x0001 /* overrun error bit */ 158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 159 #elif defined(CONFIG_CPU_SH7770) 160 # define SCSPTR0 0xff923020 /* 16 bit SCIF */ 161 # define SCSPTR1 0xff924020 /* 16 bit SCIF */ 162 # define SCSPTR2 0xff925020 /* 16 bit SCIF */ 163 # define SCIF_ORER 0x0001 /* overrun error bit */ 164 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 165 #elif defined(CONFIG_CPU_SH7780) 166 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 167 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 168 # define SCIF_ORER 0x0001 /* Overrun error bit */ 169 170 #if defined(CONFIG_SH_SH2007) 171 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ 172 # define SCSCR_INIT(port) 0x38 173 #else 174 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ 175 # define SCSCR_INIT(port) 0x3a 176 #endif 177 178 #elif defined(CONFIG_CPU_SH7785) || \ 179 defined(CONFIG_CPU_SH7786) 180 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 181 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 182 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 183 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 184 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 185 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 186 # define SCIF_ORER 0x0001 /* Overrun error bit */ 187 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 188 #elif defined(CONFIG_CPU_SH7201) || \ 189 defined(CONFIG_CPU_SH7203) || \ 190 defined(CONFIG_CPU_SH7206) || \ 191 defined(CONFIG_CPU_SH7263) || \ 192 defined(CONFIG_CPU_SH7264) 193 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 194 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 195 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 196 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 197 # if defined(CONFIG_CPU_SH7201) 198 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 199 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 200 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 201 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 202 # endif 203 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 204 #elif defined(CONFIG_CPU_SH7269) 205 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ 206 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ 207 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ 208 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */ 209 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */ 210 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */ 211 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ 212 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ 213 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 214 #elif defined(CONFIG_CPU_SH7619) 215 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 216 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 217 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 218 # define SCIF_ORER 0x0001 /* overrun error bit */ 219 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 220 #elif defined(CONFIG_CPU_SHX3) 221 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 222 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 223 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 224 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 225 # define SCIF_ORER 0x0001 /* Overrun error bit */ 226 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 227 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 228 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 229 # if defined(CONFIG_SCIF_A) 230 # define SCIF_ORER 0x0200 231 # else 232 # define SCIF_ORER 0x0001 233 # endif 234 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) 235 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ 236 #else 237 # error CPU subtype not defined 238 #endif 239 240 /* SCSCR */ 241 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 242 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 243 #define SCI_CTRL_FLAGS_TE 0x20 /* all */ 244 #define SCI_CTRL_FLAGS_RE 0x10 /* all */ 245 #if defined(CONFIG_CPU_SH7750) || \ 246 defined(CONFIG_CPU_SH7091) || \ 247 defined(CONFIG_CPU_SH7750R) || \ 248 defined(CONFIG_CPU_SH7722) || \ 249 defined(CONFIG_CPU_SH7734) || \ 250 defined(CONFIG_CPU_SH7750S) || \ 251 defined(CONFIG_CPU_SH7751) || \ 252 defined(CONFIG_CPU_SH7751R) || \ 253 defined(CONFIG_CPU_SH7763) || \ 254 defined(CONFIG_CPU_SH7780) || \ 255 defined(CONFIG_CPU_SH7785) || \ 256 defined(CONFIG_CPU_SH7786) || \ 257 defined(CONFIG_CPU_SHX3) 258 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 259 #elif defined(CONFIG_CPU_SH7724) 260 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) 261 #else 262 #define SCI_CTRL_FLAGS_REIE 0 263 #endif 264 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 265 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 266 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 267 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 268 269 /* SCxSR SCI */ 270 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 271 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 272 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 273 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 274 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 275 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 276 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 277 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 278 279 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 280 281 /* SCxSR SCIF */ 282 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 283 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 284 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 285 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 286 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 287 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 288 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 289 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 290 291 #if defined(CONFIG_CPU_SH7705) || \ 292 defined(CONFIG_CPU_SH7720) || \ 293 defined(CONFIG_CPU_SH7721) || \ 294 defined(CONFIG_ARCH_SH7367) || \ 295 defined(CONFIG_ARCH_SH7377) || \ 296 defined(CONFIG_ARCH_SH7372) || \ 297 defined(CONFIG_SH73A0) || \ 298 defined(CONFIG_R8A7740) 299 # define SCIF_ORER 0x0200 300 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 301 # define SCIF_RFDC_MASK 0x007f 302 # define SCIF_TXROOM_MAX 64 303 #elif defined(CONFIG_CPU_SH7763) 304 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 305 # define SCIF_RFDC_MASK 0x007f 306 # define SCIF_TXROOM_MAX 64 307 /* SH7763 SCIF2 support */ 308 # define SCIF2_RFDC_MASK 0x001f 309 # define SCIF2_TXROOM_MAX 16 310 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 311 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 312 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 313 # if defined(CONFIG_SCIF_A) 314 # define SCIF_RFDC_MASK 0x007f 315 # else 316 # define SCIF_RFDC_MASK 0x001f 317 # endif 318 #else 319 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 320 # define SCIF_RFDC_MASK 0x001f 321 # define SCIF_TXROOM_MAX 16 322 #endif 323 324 #ifndef SCIF_ORER 325 #define SCIF_ORER 0x0000 326 #endif 327 328 #define SCxSR_TEND(port)\ 329 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 330 #define SCxSR_ERRORS(port)\ 331 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 332 #define SCxSR_RDxF(port)\ 333 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 334 #define SCxSR_TDxE(port)\ 335 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 336 #define SCxSR_FER(port)\ 337 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 338 #define SCxSR_PER(port)\ 339 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 340 #define SCxSR_BRK(port)\ 341 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 342 #define SCxSR_ORER(port)\ 343 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 344 345 #if defined(CONFIG_CPU_SH7705) || \ 346 defined(CONFIG_CPU_SH7720) || \ 347 defined(CONFIG_CPU_SH7721) || \ 348 defined(CONFIG_ARCH_SH7367) || \ 349 defined(CONFIG_ARCH_SH7377) || \ 350 defined(CONFIG_ARCH_SH7372) || \ 351 defined(CONFIG_SH73A0) || \ 352 defined(CONFIG_R8A7740) 353 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 354 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 355 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 356 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 357 #else 358 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 359 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 360 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 361 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 362 #endif 363 364 /* SCFCR */ 365 #define SCFCR_RFRST 0x0002 366 #define SCFCR_TFRST 0x0004 367 #define SCFCR_TCRST 0x4000 368 #define SCFCR_MCE 0x0008 369 370 #define SCI_MAJOR 204 371 #define SCI_MINOR_START 8 372 373 /* Generic serial flags */ 374 #define SCI_RX_THROTTLE 0x0000001 375 376 #define SCI_MAGIC 0xbabeface 377 378 /* 379 * Events are used to schedule things to happen at timer-interrupt 380 * time, instead of at rs interrupt time. 381 */ 382 #define SCI_EVENT_WRITE_WAKEUP 0 383 384 #define SCI_IN(size, offset)\ 385 if ((size) == 8) {\ 386 return readb(port->membase + (offset));\ 387 } else {\ 388 return readw(port->membase + (offset));\ 389 } 390 #define SCI_OUT(size, offset, value)\ 391 if ((size) == 8) {\ 392 writeb(value, port->membase + (offset));\ 393 } else if ((size) == 16) {\ 394 writew(value, port->membase + (offset));\ 395 } 396 397 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 398 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 399 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 400 SCI_IN(scif_size, scif_offset)\ 401 } else { /* PORT_SCI or PORT_SCIFA */\ 402 SCI_IN(sci_size, sci_offset);\ 403 }\ 404 }\ 405 static inline void sci_##name##_out(struct uart_port *port,\ 406 unsigned int value) {\ 407 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ 408 SCI_OUT(scif_size, scif_offset, value)\ 409 } else { /* PORT_SCI or PORT_SCIFA */\ 410 SCI_OUT(sci_size, sci_offset, value);\ 411 }\ 412 } 413 414 #ifdef CONFIG_H8300 415 /* h8300 don't have SCIF */ 416 #define CPU_SCIF_FNS(name) \ 417 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 418 return 0;\ 419 }\ 420 static inline void sci_##name##_out(struct uart_port *port,\ 421 unsigned int value) {\ 422 } 423 #else 424 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 425 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 426 SCI_IN(scif_size, scif_offset);\ 427 }\ 428 static inline void sci_##name##_out(struct uart_port *port,\ 429 unsigned int value) {\ 430 SCI_OUT(scif_size, scif_offset, value);\ 431 } 432 #endif 433 434 #define CPU_SCI_FNS(name, sci_offset, sci_size)\ 435 static inline unsigned int sci_##name##_in(struct uart_port *port) {\ 436 SCI_IN(sci_size, sci_offset);\ 437 }\ 438 static inline void sci_##name##_out(struct uart_port *port,\ 439 unsigned int value) {\ 440 SCI_OUT(sci_size, sci_offset, value);\ 441 } 442 443 #if defined(CONFIG_CPU_SH3) || \ 444 defined(CONFIG_ARCH_SH7367) || \ 445 defined(CONFIG_ARCH_SH7377) || \ 446 defined(CONFIG_ARCH_SH7372) || \ 447 defined(CONFIG_SH73A0) || \ 448 defined(CONFIG_R8A7740) 449 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) 450 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 451 sh4_sci_offset, sh4_sci_size, \ 452 sh3_scif_offset, sh3_scif_size, \ 453 sh4_scif_offset, sh4_scif_size, \ 454 h8_sci_offset, h8_sci_size) \ 455 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 456 sh4_scif_offset, sh4_scif_size) 457 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 458 sh4_scif_offset, sh4_scif_size) \ 459 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 460 #elif defined(CONFIG_CPU_SH7705) || \ 461 defined(CONFIG_CPU_SH7720) || \ 462 defined(CONFIG_CPU_SH7721) || \ 463 defined(CONFIG_ARCH_SH7367) || \ 464 defined(CONFIG_ARCH_SH7377) || \ 465 defined(CONFIG_SH73A0) 466 #define SCIF_FNS(name, scif_offset, scif_size) \ 467 CPU_SCIF_FNS(name, scif_offset, scif_size) 468 #elif defined(CONFIG_ARCH_SH7372) || \ 469 defined(CONFIG_R8A7740) 470 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 471 sh4_scifb_offset, sh4_scifb_size) \ 472 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 473 sh4_scifb_offset, sh4_scifb_size) 474 #define SCIF_FNS(name, scif_offset, scif_size) \ 475 CPU_SCIF_FNS(name, scif_offset, scif_size) 476 #else 477 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 478 sh4_sci_offset, sh4_sci_size, \ 479 sh3_scif_offset, sh3_scif_size,\ 480 sh4_scif_offset, sh4_scif_size, \ 481 h8_sci_offset, h8_sci_size) \ 482 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 483 sh3_scif_offset, sh3_scif_size) 484 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 485 sh4_scif_offset, sh4_scif_size) \ 486 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 487 #endif 488 #elif defined(__H8300H__) || defined(__H8300S__) 489 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 490 sh4_sci_offset, sh4_sci_size, \ 491 sh3_scif_offset, sh3_scif_size,\ 492 sh4_scif_offset, sh4_scif_size, \ 493 h8_sci_offset, h8_sci_size) \ 494 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 495 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ 496 sh4_scif_offset, sh4_scif_size) \ 497 CPU_SCIF_FNS(name) 498 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) 499 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 500 sh4_scif_offset, sh4_scif_size) \ 501 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ 502 sh4_scif_offset, sh4_scif_size) 503 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 504 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 505 #else 506 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ 507 sh4_sci_offset, sh4_sci_size, \ 508 sh3_scif_offset, sh3_scif_size,\ 509 sh4_scif_offset, sh4_scif_size, \ 510 h8_sci_offset, h8_sci_size) \ 511 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ 512 sh4_scif_offset, sh4_scif_size) 513 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ 514 sh4_scif_offset, sh4_scif_size) \ 515 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 516 #endif 517 518 #if defined(CONFIG_CPU_SH7705) || \ 519 defined(CONFIG_CPU_SH7720) || \ 520 defined(CONFIG_CPU_SH7721) || \ 521 defined(CONFIG_ARCH_SH7367) || \ 522 defined(CONFIG_ARCH_SH7377) || \ 523 defined(CONFIG_SH73A0) 524 525 SCIF_FNS(SCSMR, 0x00, 16) 526 SCIF_FNS(SCBRR, 0x04, 8) 527 SCIF_FNS(SCSCR, 0x08, 16) 528 SCIF_FNS(SCTDSR, 0x0c, 8) 529 SCIF_FNS(SCFER, 0x10, 16) 530 SCIF_FNS(SCxSR, 0x14, 16) 531 SCIF_FNS(SCFCR, 0x18, 16) 532 SCIF_FNS(SCFDR, 0x1c, 16) 533 SCIF_FNS(SCxTDR, 0x20, 8) 534 SCIF_FNS(SCxRDR, 0x24, 8) 535 SCIF_FNS(SCLSR, 0x00, 0) 536 SCIF_FNS(DL, 0x00, 0) /* dummy */ 537 #elif defined(CONFIG_ARCH_SH7372) || \ 538 defined(CONFIG_R8A7740) 539 SCIF_FNS(SCSMR, 0x00, 16) 540 SCIF_FNS(SCBRR, 0x04, 8) 541 SCIF_FNS(SCSCR, 0x08, 16) 542 SCIF_FNS(SCTDSR, 0x0c, 16) 543 SCIF_FNS(SCFER, 0x10, 16) 544 SCIF_FNS(SCxSR, 0x14, 16) 545 SCIF_FNS(SCFCR, 0x18, 16) 546 SCIF_FNS(SCFDR, 0x1c, 16) 547 SCIF_FNS(SCTFDR, 0x38, 16) 548 SCIF_FNS(SCRFDR, 0x3c, 16) 549 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 550 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 551 SCIF_FNS(SCLSR, 0x00, 0) 552 SCIF_FNS(DL, 0x00, 0) /* dummy */ 553 #elif defined(CONFIG_CPU_SH7723) ||\ 554 defined(CONFIG_CPU_SH7724) 555 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 556 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 557 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 558 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 559 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 560 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 561 SCIx_FNS(SCSPTR, 0, 0, 0, 0) 562 SCIF_FNS(SCTDSR, 0x0c, 8) 563 SCIF_FNS(SCFER, 0x10, 16) 564 SCIF_FNS(SCFCR, 0x18, 16) 565 SCIF_FNS(SCFDR, 0x1c, 16) 566 SCIF_FNS(SCLSR, 0x24, 16) 567 SCIF_FNS(DL, 0x00, 0) /* dummy */ 568 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 569 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 570 /* SCIFA and SCIF register offsets and size */ 571 SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0) 572 SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0) 573 SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0) 574 SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0) 575 SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0) 576 SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0) 577 SCIF_FNS(SCFCR, 0, 0, 0x18, 16) 578 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 579 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 580 SCIF_FNS(DL, 0, 0, 0x30, 16) 581 SCIF_FNS(CKS, 0, 0, 0x34, 16) 582 #if defined(CONFIG_SCIF_A) 583 SCIF_FNS(SCLSR, 0, 0, 0x14, 16) 584 #else 585 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 586 #endif 587 #else 588 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 589 /* name off sz off sz off sz off sz off sz*/ 590 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 591 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 592 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 593 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 594 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 595 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 596 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 597 #if defined(CONFIG_CPU_SH7760) || \ 598 defined(CONFIG_CPU_SH7780) || \ 599 defined(CONFIG_CPU_SH7785) || \ 600 defined(CONFIG_CPU_SH7786) 601 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 602 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 603 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 604 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 605 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 606 #elif defined(CONFIG_CPU_SH7763) 607 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 608 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 609 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) 610 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 611 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 612 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 613 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 614 #else 615 616 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 617 #if defined(CONFIG_CPU_SH7722) 618 SCIF_FNS(SCSPTR, 0, 0, 0, 0) 619 #else 620 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 621 #endif 622 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 623 #endif 624 SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ 625 #endif 626 #define sci_in(port, reg) sci_##reg##_in(port) 627 #define sci_out(port, reg, value) sci_##reg##_out(port, value) 628 629 /* H8/300 series SCI pins assignment */ 630 #if defined(__H8300H__) || defined(__H8300S__) 631 static const struct __attribute__((packed)) { 632 int port; /* GPIO port no */ 633 unsigned short rx, tx; /* GPIO bit no */ 634 } h8300_sci_pins[] = { 635 #if defined(CONFIG_H83007) || defined(CONFIG_H83068) 636 { /* SCI0 */ 637 .port = H8300_GPIO_P9, 638 .rx = H8300_GPIO_B2, 639 .tx = H8300_GPIO_B0, 640 }, 641 { /* SCI1 */ 642 .port = H8300_GPIO_P9, 643 .rx = H8300_GPIO_B3, 644 .tx = H8300_GPIO_B1, 645 }, 646 { /* SCI2 */ 647 .port = H8300_GPIO_PB, 648 .rx = H8300_GPIO_B7, 649 .tx = H8300_GPIO_B6, 650 } 651 #elif defined(CONFIG_H8S2678) 652 { /* SCI0 */ 653 .port = H8300_GPIO_P3, 654 .rx = H8300_GPIO_B2, 655 .tx = H8300_GPIO_B0, 656 }, 657 { /* SCI1 */ 658 .port = H8300_GPIO_P3, 659 .rx = H8300_GPIO_B3, 660 .tx = H8300_GPIO_B1, 661 }, 662 { /* SCI2 */ 663 .port = H8300_GPIO_P5, 664 .rx = H8300_GPIO_B1, 665 .tx = H8300_GPIO_B0, 666 } 667 #endif 668 }; 669 #endif 670 671 #if defined(CONFIG_CPU_SH7706) || \ 672 defined(CONFIG_CPU_SH7707) || \ 673 defined(CONFIG_CPU_SH7708) || \ 674 defined(CONFIG_CPU_SH7709) 675 static inline int sci_rxd_in(struct uart_port *port) 676 { 677 if (port->mapbase == 0xfffffe80) 678 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 679 return 1; 680 } 681 #elif defined(CONFIG_CPU_SH7750) || \ 682 defined(CONFIG_CPU_SH7751) || \ 683 defined(CONFIG_CPU_SH7751R) || \ 684 defined(CONFIG_CPU_SH7750R) || \ 685 defined(CONFIG_CPU_SH7750S) || \ 686 defined(CONFIG_CPU_SH7091) 687 static inline int sci_rxd_in(struct uart_port *port) 688 { 689 if (port->mapbase == 0xffe00000) 690 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 691 return 1; 692 } 693 #elif defined(__H8300H__) || defined(__H8300S__) 694 static inline int sci_rxd_in(struct uart_port *port) 695 { 696 int ch = (port->mapbase - SMR0) >> 3; 697 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 698 } 699 #else /* default case for non-SCI processors */ 700 static inline int sci_rxd_in(struct uart_port *port) 701 { 702 return 1; 703 } 704 #endif 705 706 /* 707 * Values for the BitRate Register (SCBRR) 708 * 709 * The values are actually divisors for a frequency which can 710 * be internal to the SH3 (14.7456MHz) or derived from an external 711 * clock source. This driver assumes the internal clock is used; 712 * to support using an external clock source, config options or 713 * possibly command-line options would need to be added. 714 * 715 * Also, to support speeds below 2400 (why?) the lower 2 bits of 716 * the SCSMR register would also need to be set to non-zero values. 717 * 718 * -- Greg Banks 27Feb2000 719 * 720 * Answer: The SCBRR register is only eight bits, and the value in 721 * it gets larger with lower baud rates. At around 2400 (depending on 722 * the peripherial module clock) you run out of bits. However the 723 * lower two bits of SCSMR allow the module clock to be divided down, 724 * scaling the value which is needed in SCBRR. 725 * 726 * -- Stuart Menefy - 23 May 2000 727 * 728 * I meant, why would anyone bother with bitrates below 2400. 729 * 730 * -- Greg Banks - 7Jul2000 731 * 732 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 733 * tape reader as a console! 734 * 735 * -- Mitch Davis - 15 Jul 2000 736 */ 737 738 #if (defined(CONFIG_CPU_SH7780) || \ 739 defined(CONFIG_CPU_SH7785) || \ 740 defined(CONFIG_CPU_SH7786)) && \ 741 !defined(CONFIG_SH_SH2007) 742 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 743 #elif defined(CONFIG_CPU_SH7705) || \ 744 defined(CONFIG_CPU_SH7720) || \ 745 defined(CONFIG_CPU_SH7721) || \ 746 defined(CONFIG_ARCH_SH7367) || \ 747 defined(CONFIG_ARCH_SH7377) || \ 748 defined(CONFIG_ARCH_SH7372) || \ 749 defined(CONFIG_SH73A0) || \ 750 defined(CONFIG_R8A7740) 751 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 752 #elif defined(CONFIG_CPU_SH7723) ||\ 753 defined(CONFIG_CPU_SH7724) 754 static inline int scbrr_calc(struct uart_port *port, int bps, int clk) 755 { 756 if (port->type == PORT_SCIF) 757 return (clk+16*bps)/(32*bps)-1; 758 else 759 return ((clk*2)+16*bps)/(16*bps)-1; 760 } 761 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) 762 #elif defined(__H8300H__) || defined(__H8300S__) 763 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) 764 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 765 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 766 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ 767 #if defined(CONFIG_SCIF_A) 768 #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ 769 #else 770 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ 771 #endif 772 #else /* Generic SH */ 773 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 774 #endif 775 776 #ifndef DL_VALUE 777 #define DL_VALUE(bps, clk) 0 778 #endif 779