1 /* 2 * SuperH SCIF device driver. 3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <asm/processor.h> 22 23 #ifdef CFG_SCIF_CONSOLE 24 25 #if defined (CONFIG_CONS_SCIF0) 26 #define SCIF_BASE SCIF0_BASE 27 #elif defined (CONFIG_CONS_SCIF1) 28 #define SCIF_BASE SCIF1_BASE 29 #else 30 #error "Default SCIF doesn't set....." 31 #endif 32 33 /* Base register */ 34 #define SCSMR (vu_short *)(SCIF_BASE + 0x0) 35 #define SCBRR (vu_char *)(SCIF_BASE + 0x4) 36 #define SCSCR (vu_short *)(SCIF_BASE + 0x8) 37 #define SCFCR (vu_short *)(SCIF_BASE + 0x18) 38 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) 39 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ 40 #define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ 41 #define SCFTDR (vu_char *)(SCIF_BASE + 0x20) 42 #define SCFRDR (vu_char *)(SCIF_BASE + 0x24) 43 #else 44 #define SCFTDR (vu_char *)(SCIF_BASE + 0xC) 45 #define SCFSR (vu_short *)(SCIF_BASE + 0x10) 46 #define SCFRDR (vu_char *)(SCIF_BASE + 0x14) 47 #endif 48 49 #if defined(CONFIG_SH4A) 50 #define SCRFDR (vu_short *)(SCIF_BASE + 0x20) 51 #define SCSPTR (vu_short *)(SCIF_BASE + 0x24) 52 #define SCLSR (vu_short *)(SCIF_BASE + 0x28) 53 #define SCRER (vu_short *)(SCIF_BASE + 0x2C) 54 #define LSR_ORER 1 55 #elif defined (CONFIG_SH4) 56 #define SCSPTR (vu_short *)(SCIF_BASE + 0x20) 57 #define SCLSR (vu_short *)(SCIF_BASE + 0x24) 58 #define LSR_ORER 1 59 #elif defined (CONFIG_SH3) 60 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ 61 #define SCLSR (vu_short *)(SCIF_BASE + 0x24) 62 #define LSR_ORER 0x0200 63 #else 64 #define SCLSR SCFSR /* SCSSR */ 65 #define LSR_ORER 1 66 #endif 67 #endif 68 69 #if defined(CONFIG_CPU_SH7720) 70 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 71 #else /* Generic SuperH */ 72 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 73 #endif 74 75 #define SCR_RE (1 << 4) 76 #define SCR_TE (1 << 5) 77 #define FCR_RFRST (1 << 1) /* RFCL */ 78 #define FCR_TFRST (1 << 2) /* TFCL */ 79 #define FSR_DR (1 << 0) 80 #define FSR_RDF (1 << 1) 81 #define FSR_FER (1 << 3) 82 #define FSR_BRK (1 << 4) 83 #define FSR_FER (1 << 3) 84 #define FSR_TEND (1 << 6) 85 #define FSR_ER (1 << 7) 86 87 /*----------------------------------------------------------------------*/ 88 89 void serial_setbrg (void) 90 { 91 DECLARE_GLOBAL_DATA_PTR; 92 *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ); 93 } 94 95 int serial_init (void) 96 { 97 *SCSCR = (SCR_RE | SCR_TE); 98 *SCSMR = 0 ; 99 *SCSMR = 0; 100 *SCFCR = (FCR_RFRST | FCR_TFRST); 101 *SCFCR; 102 *SCFCR = 0; 103 104 serial_setbrg(); 105 return 0; 106 } 107 108 static int serial_tx_fifo_level (void) 109 { 110 return (*SCFDR >> 8) & 0x1F; 111 } 112 113 static int serial_rx_fifo_level (void) 114 { 115 return (*SCFDR >> 0) & 0x1F; 116 } 117 118 void serial_raw_putc (const char c) 119 { 120 unsigned int fsr_bits_to_clear; 121 122 while (1) { 123 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ 124 fsr_bits_to_clear = FSR_TEND; 125 break; 126 } 127 } 128 129 *SCFTDR = c; 130 if (fsr_bits_to_clear != 0) 131 *SCFSR &= ~fsr_bits_to_clear; 132 } 133 134 void serial_putc (const char c) 135 { 136 if (c == '\n') 137 serial_raw_putc ('\r'); 138 serial_raw_putc (c); 139 } 140 141 void serial_puts (const char *s) 142 { 143 char c; 144 while ((c = *s++) != 0) 145 serial_putc (c); 146 } 147 148 int serial_tstc (void) 149 { 150 return serial_rx_fifo_level() ? 1 : 0; 151 } 152 153 #define FSR_ERR_CLEAR 0x0063 154 #define RDRF_CLEAR 0x00fc 155 void handle_error( void ){ 156 157 (void)*SCFSR ; 158 *SCFSR = FSR_ERR_CLEAR ; 159 (void)*SCLSR ; 160 *SCLSR = 0x00 ; 161 } 162 163 int serial_getc_check( void ){ 164 unsigned short status; 165 166 status = *SCFSR ; 167 168 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 169 handle_error(); 170 if( *SCLSR & LSR_ORER ) 171 handle_error(); 172 return (status & ( FSR_DR | FSR_RDF )); 173 } 174 175 int serial_getc (void) 176 { 177 unsigned short status ; 178 char ch; 179 while(!serial_getc_check()); 180 181 ch = *SCFRDR; 182 status = *SCFSR ; 183 184 *SCFSR = RDRF_CLEAR ; 185 186 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 187 handle_error(); 188 189 if( *SCLSR & LSR_ORER ) 190 handle_error(); 191 192 return ch ; 193 } 194 195 #endif /* CFG_SCIF_CONSOLE */ 196