1 /* 2 * SuperH SCIF device driver. 3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <asm/processor.h> 22 23 #ifdef CFG_SCIF_CONSOLE 24 25 #if defined (CONFIG_CONS_SCIF0) 26 #define SCIF_BASE SCIF0_BASE 27 #elif defined (CONFIG_CONS_SCIF1) 28 #define SCIF_BASE SCIF1_BASE 29 #else 30 #error "Default SCIF doesn't set....." 31 #endif 32 33 /* Base register */ 34 #define SCSMR (vu_short *)(SCIF_BASE + 0x0) 35 #define SCBRR (vu_char *)(SCIF_BASE + 0x4) 36 #define SCSCR (vu_short *)(SCIF_BASE + 0x8) 37 #define SCFCR (vu_short *)(SCIF_BASE + 0x18) 38 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) 39 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ 40 # define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ 41 # define SCFTDR (vu_char *)(SCIF_BASE + 0x20) 42 # define SCFRDR (vu_char *)(SCIF_BASE + 0x24) 43 #else 44 # define SCFTDR (vu_char *)(SCIF_BASE + 0xC) 45 # define SCFSR (vu_short *)(SCIF_BASE + 0x10) 46 # define SCFRDR (vu_char *)(SCIF_BASE + 0x14) 47 #endif 48 49 #if defined(CONFIG_CPU_SH7780) || \ 50 defined(CONFIG_CPU_SH7785) 51 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20) 52 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24) 53 # define SCLSR (vu_short *)(SCIF_BASE + 0x28) 54 # define SCRER (vu_short *)(SCIF_BASE + 0x2C) 55 # define LSR_ORER 1 56 # define FIFOLEVEL_MASK 0xFF 57 #elif defined(CONFIG_CPU_SH7750) || \ 58 defined(CONFIG_CPU_SH7751) || \ 59 defined(CONFIG_CPU_SH7722) 60 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) 61 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 62 # define LSR_ORER 1 63 # define FIFOLEVEL_MASK 0x1F 64 #elif defined(CONFIG_CPU_SH7720) 65 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 66 # define LSR_ORER 0x0200 67 # define FIFOLEVEL_MASK 0x1F 68 #elif defined(CONFIG_CPU_SH7710) 69 defined(CONFIG_CPU_SH7712) 70 # define SCLSR SCFSR /* SCSSR */ 71 # define LSR_ORER 1 72 # define FIFOLEVEL_MASK 0x1F 73 #endif 74 75 /* SCBRR register value setting */ 76 #if defined(CONFIG_CPU_SH7720) 77 # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 78 #else /* Generic SuperH */ 79 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 80 #endif 81 82 #define SCR_RE (1 << 4) 83 #define SCR_TE (1 << 5) 84 #define FCR_RFRST (1 << 1) /* RFCL */ 85 #define FCR_TFRST (1 << 2) /* TFCL */ 86 #define FSR_DR (1 << 0) 87 #define FSR_RDF (1 << 1) 88 #define FSR_FER (1 << 3) 89 #define FSR_BRK (1 << 4) 90 #define FSR_FER (1 << 3) 91 #define FSR_TEND (1 << 6) 92 #define FSR_ER (1 << 7) 93 94 /*----------------------------------------------------------------------*/ 95 96 void serial_setbrg (void) 97 { 98 DECLARE_GLOBAL_DATA_PTR; 99 *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ); 100 } 101 102 int serial_init (void) 103 { 104 *SCSCR = (SCR_RE | SCR_TE); 105 *SCSMR = 0 ; 106 *SCSMR = 0; 107 *SCFCR = (FCR_RFRST | FCR_TFRST); 108 *SCFCR; 109 *SCFCR = 0; 110 111 serial_setbrg(); 112 return 0; 113 } 114 115 static int serial_rx_fifo_level (void) 116 { 117 #if defined(CONFIG_SH4A) 118 return (*SCRFDR >> 0) & FIFOLEVEL_MASK; 119 #else 120 return (*SCFDR >> 0) & FIFOLEVEL_MASK; 121 #endif 122 } 123 124 void serial_raw_putc (const char c) 125 { 126 unsigned int fsr_bits_to_clear; 127 128 while (1) { 129 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ 130 fsr_bits_to_clear = FSR_TEND; 131 break; 132 } 133 } 134 135 *SCFTDR = c; 136 if (fsr_bits_to_clear != 0) 137 *SCFSR &= ~fsr_bits_to_clear; 138 } 139 140 void serial_putc (const char c) 141 { 142 if (c == '\n') 143 serial_raw_putc ('\r'); 144 serial_raw_putc (c); 145 } 146 147 void serial_puts (const char *s) 148 { 149 char c; 150 while ((c = *s++) != 0) 151 serial_putc (c); 152 } 153 154 int serial_tstc (void) 155 { 156 return serial_rx_fifo_level() ? 1 : 0; 157 } 158 159 #define FSR_ERR_CLEAR 0x0063 160 #define RDRF_CLEAR 0x00fc 161 void handle_error( void ){ 162 163 (void)*SCFSR ; 164 *SCFSR = FSR_ERR_CLEAR ; 165 (void)*SCLSR ; 166 *SCLSR = 0x00 ; 167 } 168 169 int serial_getc_check( void ){ 170 unsigned short status; 171 172 status = *SCFSR ; 173 174 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 175 handle_error(); 176 if( *SCLSR & LSR_ORER ) 177 handle_error(); 178 return (status & ( FSR_DR | FSR_RDF )); 179 } 180 181 int serial_getc (void) 182 { 183 unsigned short status ; 184 char ch; 185 while(!serial_getc_check()); 186 187 ch = *SCFRDR; 188 status = *SCFSR ; 189 190 *SCFSR = RDRF_CLEAR ; 191 192 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 193 handle_error(); 194 195 if( *SCLSR & LSR_ORER ) 196 handle_error(); 197 198 return ch ; 199 } 200 201 #endif /* CFG_SCIF_CONSOLE */ 202