1 /* 2 * SuperH SCIF device driver. 3 * Copyright (C) 2013 Renesas Electronics Corporation 4 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu 5 * Copyright (C) 2002 - 2008 Paul Mundt 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <errno.h> 12 #include <dm.h> 13 #include <asm/io.h> 14 #include <asm/processor.h> 15 #include <serial.h> 16 #include <linux/compiler.h> 17 #include <dm/platform_data/serial_sh.h> 18 #include "serial_sh.h" 19 20 #if defined(CONFIG_CPU_SH7760) || \ 21 defined(CONFIG_CPU_SH7780) || \ 22 defined(CONFIG_CPU_SH7785) || \ 23 defined(CONFIG_CPU_SH7786) 24 static int scif_rxfill(struct uart_port *port) 25 { 26 return sci_in(port, SCRFDR) & 0xff; 27 } 28 #elif defined(CONFIG_CPU_SH7763) 29 static int scif_rxfill(struct uart_port *port) 30 { 31 if ((port->mapbase == 0xffe00000) || 32 (port->mapbase == 0xffe08000)) { 33 /* SCIF0/1*/ 34 return sci_in(port, SCRFDR) & 0xff; 35 } else { 36 /* SCIF2 */ 37 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; 38 } 39 } 40 #elif defined(CONFIG_ARCH_SH7372) 41 static int scif_rxfill(struct uart_port *port) 42 { 43 if (port->type == PORT_SCIFA) 44 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 45 else 46 return sci_in(port, SCRFDR); 47 } 48 #else 49 static int scif_rxfill(struct uart_port *port) 50 { 51 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 52 } 53 #endif 54 55 static void sh_serial_init_generic(struct uart_port *port) 56 { 57 sci_out(port, SCSCR , SCSCR_INIT(port)); 58 sci_out(port, SCSCR , SCSCR_INIT(port)); 59 sci_out(port, SCSMR, 0); 60 sci_out(port, SCSMR, 0); 61 sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST); 62 sci_in(port, SCFCR); 63 sci_out(port, SCFCR, 0); 64 } 65 66 static void 67 sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate) 68 { 69 if (port->clk_mode == EXT_CLK) { 70 unsigned short dl = DL_VALUE(baudrate, clk); 71 sci_out(port, DL, dl); 72 /* Need wait: Clock * 1/dl * 1/16 */ 73 udelay((1000000 * dl * 16 / clk) * 1000 + 1); 74 } else { 75 sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk)); 76 } 77 } 78 79 static void handle_error(struct uart_port *port) 80 { 81 sci_in(port, SCxSR); 82 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 83 sci_in(port, SCLSR); 84 sci_out(port, SCLSR, 0x00); 85 } 86 87 static int serial_raw_putc(struct uart_port *port, const char c) 88 { 89 /* Tx fifo is empty */ 90 if (!(sci_in(port, SCxSR) & SCxSR_TEND(port))) 91 return -EAGAIN; 92 93 sci_out(port, SCxTDR, c); 94 sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port)); 95 96 return 0; 97 } 98 99 static int serial_rx_fifo_level(struct uart_port *port) 100 { 101 return scif_rxfill(port); 102 } 103 104 static int sh_serial_tstc_generic(struct uart_port *port) 105 { 106 if (sci_in(port, SCxSR) & SCIF_ERRORS) { 107 handle_error(port); 108 return 0; 109 } 110 111 return serial_rx_fifo_level(port) ? 1 : 0; 112 } 113 114 static int serial_getc_check(struct uart_port *port) 115 { 116 unsigned short status; 117 118 status = sci_in(port, SCxSR); 119 120 if (status & SCIF_ERRORS) 121 handle_error(port); 122 if (sci_in(port, SCLSR) & SCxSR_ORER(port)) 123 handle_error(port); 124 return status & (SCIF_DR | SCxSR_RDxF(port)); 125 } 126 127 static int sh_serial_getc_generic(struct uart_port *port) 128 { 129 unsigned short status; 130 char ch; 131 132 if (!serial_getc_check(port)) 133 return -EAGAIN; 134 135 ch = sci_in(port, SCxRDR); 136 status = sci_in(port, SCxSR); 137 138 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 139 140 if (status & SCIF_ERRORS) 141 handle_error(port); 142 143 if (sci_in(port, SCLSR) & SCxSR_ORER(port)) 144 handle_error(port); 145 146 return ch; 147 } 148 149 #ifdef CONFIG_DM_SERIAL 150 151 static int sh_serial_pending(struct udevice *dev, bool input) 152 { 153 struct uart_port *priv = dev_get_priv(dev); 154 155 return sh_serial_tstc_generic(priv); 156 } 157 158 static int sh_serial_putc(struct udevice *dev, const char ch) 159 { 160 struct uart_port *priv = dev_get_priv(dev); 161 162 return serial_raw_putc(priv, ch); 163 } 164 165 static int sh_serial_getc(struct udevice *dev) 166 { 167 struct uart_port *priv = dev_get_priv(dev); 168 169 return sh_serial_getc_generic(priv); 170 } 171 172 static int sh_serial_setbrg(struct udevice *dev, int baudrate) 173 { 174 struct sh_serial_platdata *plat = dev_get_platdata(dev); 175 struct uart_port *priv = dev_get_priv(dev); 176 177 sh_serial_setbrg_generic(priv, plat->clk, baudrate); 178 179 return 0; 180 } 181 182 static int sh_serial_probe(struct udevice *dev) 183 { 184 struct sh_serial_platdata *plat = dev_get_platdata(dev); 185 struct uart_port *priv = dev_get_priv(dev); 186 187 priv->membase = (unsigned char *)plat->base; 188 priv->mapbase = plat->base; 189 priv->type = plat->type; 190 priv->clk_mode = plat->clk_mode; 191 192 sh_serial_init_generic(priv); 193 194 return 0; 195 } 196 197 static const struct dm_serial_ops sh_serial_ops = { 198 .putc = sh_serial_putc, 199 .pending = sh_serial_pending, 200 .getc = sh_serial_getc, 201 .setbrg = sh_serial_setbrg, 202 }; 203 204 U_BOOT_DRIVER(serial_sh) = { 205 .name = "serial_sh", 206 .id = UCLASS_SERIAL, 207 .probe = sh_serial_probe, 208 .ops = &sh_serial_ops, 209 .flags = DM_FLAG_PRE_RELOC, 210 .priv_auto_alloc_size = sizeof(struct uart_port), 211 }; 212 213 #else /* CONFIG_DM_SERIAL */ 214 215 #if defined(CONFIG_CONS_SCIF0) 216 # define SCIF_BASE SCIF0_BASE 217 #elif defined(CONFIG_CONS_SCIF1) 218 # define SCIF_BASE SCIF1_BASE 219 #elif defined(CONFIG_CONS_SCIF2) 220 # define SCIF_BASE SCIF2_BASE 221 #elif defined(CONFIG_CONS_SCIF3) 222 # define SCIF_BASE SCIF3_BASE 223 #elif defined(CONFIG_CONS_SCIF4) 224 # define SCIF_BASE SCIF4_BASE 225 #elif defined(CONFIG_CONS_SCIF5) 226 # define SCIF_BASE SCIF5_BASE 227 #elif defined(CONFIG_CONS_SCIF6) 228 # define SCIF_BASE SCIF6_BASE 229 #elif defined(CONFIG_CONS_SCIF7) 230 # define SCIF_BASE SCIF7_BASE 231 #else 232 # error "Default SCIF doesn't set....." 233 #endif 234 235 #if defined(CONFIG_SCIF_A) 236 #define SCIF_BASE_PORT PORT_SCIFA 237 #else 238 #define SCIF_BASE_PORT PORT_SCIF 239 #endif 240 241 static struct uart_port sh_sci = { 242 .membase = (unsigned char *)SCIF_BASE, 243 .mapbase = SCIF_BASE, 244 .type = SCIF_BASE_PORT, 245 #ifdef CONFIG_SCIF_USE_EXT_CLK 246 .clk_mode = EXT_CLK, 247 #endif 248 }; 249 250 static void sh_serial_setbrg(void) 251 { 252 DECLARE_GLOBAL_DATA_PTR; 253 struct uart_port *port = &sh_sci; 254 255 sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate); 256 } 257 258 static int sh_serial_init(void) 259 { 260 struct uart_port *port = &sh_sci; 261 262 sh_serial_init_generic(port); 263 serial_setbrg(); 264 265 return 0; 266 } 267 268 static void sh_serial_putc(const char c) 269 { 270 struct uart_port *port = &sh_sci; 271 272 if (c == '\n') { 273 while (1) { 274 if (serial_raw_putc(port, '\r') != -EAGAIN) 275 break; 276 } 277 } 278 while (1) { 279 if (serial_raw_putc(port, c) != -EAGAIN) 280 break; 281 } 282 } 283 284 static int sh_serial_tstc(void) 285 { 286 struct uart_port *port = &sh_sci; 287 288 return sh_serial_tstc_generic(port); 289 } 290 291 static int sh_serial_getc(void) 292 { 293 struct uart_port *port = &sh_sci; 294 int ch; 295 296 while (1) { 297 ch = sh_serial_getc_generic(port); 298 if (ch != -EAGAIN) 299 break; 300 } 301 302 return ch; 303 } 304 305 static struct serial_device sh_serial_drv = { 306 .name = "sh_serial", 307 .start = sh_serial_init, 308 .stop = NULL, 309 .setbrg = sh_serial_setbrg, 310 .putc = sh_serial_putc, 311 .puts = default_serial_puts, 312 .getc = sh_serial_getc, 313 .tstc = sh_serial_tstc, 314 }; 315 316 void sh_serial_initialize(void) 317 { 318 serial_register(&sh_serial_drv); 319 } 320 321 __weak struct serial_device *default_serial_console(void) 322 { 323 return &sh_serial_drv; 324 } 325 #endif /* CONFIG_DM_SERIAL */ 326