1 /* 2 * SuperH SCIF device driver. 3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <asm/processor.h> 22 23 #ifdef CFG_SCIF_CONSOLE 24 25 #if defined (CONFIG_CONS_SCIF0) 26 #define SCIF_BASE SCIF0_BASE 27 #elif defined (CONFIG_CONS_SCIF1) 28 #define SCIF_BASE SCIF1_BASE 29 #elif defined (CONFIG_CONS_SCIF2) 30 #define SCIF_BASE SCIF2_BASE 31 #else 32 #error "Default SCIF doesn't set....." 33 #endif 34 35 /* Base register */ 36 #define SCSMR (vu_short *)(SCIF_BASE + 0x0) 37 #define SCBRR (vu_char *)(SCIF_BASE + 0x4) 38 #define SCSCR (vu_short *)(SCIF_BASE + 0x8) 39 #define SCFCR (vu_short *)(SCIF_BASE + 0x18) 40 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) 41 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ 42 # define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ 43 # define SCFTDR (vu_char *)(SCIF_BASE + 0x20) 44 # define SCFRDR (vu_char *)(SCIF_BASE + 0x24) 45 #else 46 # define SCFTDR (vu_char *)(SCIF_BASE + 0xC) 47 # define SCFSR (vu_short *)(SCIF_BASE + 0x10) 48 # define SCFRDR (vu_char *)(SCIF_BASE + 0x14) 49 #endif 50 51 #if defined(CONFIG_CPU_SH7780) || \ 52 defined(CONFIG_CPU_SH7785) 53 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20) 54 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24) 55 # define SCLSR (vu_short *)(SCIF_BASE + 0x28) 56 # define SCRER (vu_short *)(SCIF_BASE + 0x2C) 57 # define LSR_ORER 1 58 # define FIFOLEVEL_MASK 0xFF 59 #elif defined(CONFIG_CPU_SH7763) 60 # if defined (CONFIG_CONS_SCIF2) 61 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) 62 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 63 # define LSR_ORER 1 64 # define FIFOLEVEL_MASK 0x1F 65 # else 66 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20) 67 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24) 68 # define SCLSR (vu_short *)(SCIF_BASE + 0x28) 69 # define SCRER (vu_short *)(SCIF_BASE + 0x2C) 70 # define LSR_ORER 1 71 # define FIFOLEVEL_MASK 0xFF 72 # endif 73 #elif defined(CONFIG_CPU_SH7750) || \ 74 defined(CONFIG_CPU_SH7751) || \ 75 defined(CONFIG_CPU_SH7722) 76 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) 77 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 78 # define LSR_ORER 1 79 # define FIFOLEVEL_MASK 0x1F 80 #elif defined(CONFIG_CPU_SH7720) 81 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 82 # define LSR_ORER 0x0200 83 # define FIFOLEVEL_MASK 0x1F 84 #elif defined(CONFIG_CPU_SH7710) || \ 85 defined(CONFIG_CPU_SH7712) 86 # define SCLSR SCFSR /* SCSSR */ 87 # define LSR_ORER 1 88 # define FIFOLEVEL_MASK 0x1F 89 #endif 90 91 /* SCBRR register value setting */ 92 #if defined(CONFIG_CPU_SH7720) 93 # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 94 #else /* Generic SuperH */ 95 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 96 #endif 97 98 #define SCR_RE (1 << 4) 99 #define SCR_TE (1 << 5) 100 #define FCR_RFRST (1 << 1) /* RFCL */ 101 #define FCR_TFRST (1 << 2) /* TFCL */ 102 #define FSR_DR (1 << 0) 103 #define FSR_RDF (1 << 1) 104 #define FSR_FER (1 << 3) 105 #define FSR_BRK (1 << 4) 106 #define FSR_FER (1 << 3) 107 #define FSR_TEND (1 << 6) 108 #define FSR_ER (1 << 7) 109 110 /*----------------------------------------------------------------------*/ 111 112 void serial_setbrg(void) 113 { 114 DECLARE_GLOBAL_DATA_PTR; 115 *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ); 116 } 117 118 int serial_init(void) 119 { 120 *SCSCR = (SCR_RE | SCR_TE); 121 *SCSMR = 0; 122 *SCSMR = 0; 123 *SCFCR = (FCR_RFRST | FCR_TFRST); 124 *SCFCR; 125 *SCFCR = 0; 126 127 serial_setbrg(); 128 return 0; 129 } 130 131 static int serial_rx_fifo_level(void) 132 { 133 #if defined(SCRFDR) 134 return (*SCRFDR >> 0) & FIFOLEVEL_MASK; 135 #else 136 return (*SCFDR >> 0) & FIFOLEVEL_MASK; 137 #endif 138 } 139 140 void serial_raw_putc(const char c) 141 { 142 unsigned int fsr_bits_to_clear; 143 144 while (1) { 145 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ 146 fsr_bits_to_clear = FSR_TEND; 147 break; 148 } 149 } 150 151 *SCFTDR = c; 152 if (fsr_bits_to_clear != 0) 153 *SCFSR &= ~fsr_bits_to_clear; 154 } 155 156 void serial_putc(const char c) 157 { 158 if (c == '\n') 159 serial_raw_putc('\r'); 160 serial_raw_putc(c); 161 } 162 163 void serial_puts(const char *s) 164 { 165 char c; 166 while ((c = *s++) != 0) 167 serial_putc(c); 168 } 169 170 int serial_tstc(void) 171 { 172 return serial_rx_fifo_level()? 1 : 0; 173 } 174 175 #define FSR_ERR_CLEAR 0x0063 176 #define RDRF_CLEAR 0x00fc 177 void handle_error(void) 178 { 179 180 (void)*SCFSR; 181 *SCFSR = FSR_ERR_CLEAR; 182 (void)*SCLSR; 183 *SCLSR = 0x00; 184 } 185 186 int serial_getc_check(void) 187 { 188 unsigned short status; 189 190 status = *SCFSR; 191 192 if (status & (FSR_FER | FSR_ER | FSR_BRK)) 193 handle_error(); 194 if (*SCLSR & LSR_ORER) 195 handle_error(); 196 return (status & (FSR_DR | FSR_RDF)); 197 } 198 199 int serial_getc(void) 200 { 201 unsigned short status; 202 char ch; 203 while (!serial_getc_check()) ; 204 205 ch = *SCFRDR; 206 status = *SCFSR; 207 208 *SCFSR = RDRF_CLEAR; 209 210 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 211 handle_error(); 212 213 if (*SCLSR & LSR_ORER) 214 handle_error(); 215 216 return ch; 217 } 218 219 #endif /* CFG_SCIF_CONSOLE */ 220