1 /* 2 * (C) Copyright 2003, 2004 3 * ARM Ltd. 4 * Philippe Robin, <philippe.robin@arm.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * ARM PrimeCell UART's (PL010 & PL011) 11 * ------------------------------------ 12 * 13 * Definitions common to both PL010 & PL011 14 * 15 */ 16 17 #ifndef __ASSEMBLY__ 18 /* 19 * We can use a combined structure for PL010 and PL011, because they overlap 20 * only in common registers. 21 */ 22 struct pl01x_regs { 23 u32 dr; /* 0x00 Data register */ 24 u32 ecr; /* 0x04 Error clear register (Write) */ 25 u32 pl010_lcrh; /* 0x08 Line control register, high byte */ 26 u32 pl010_lcrm; /* 0x0C Line control register, middle byte */ 27 u32 pl010_lcrl; /* 0x10 Line control register, low byte */ 28 u32 pl010_cr; /* 0x14 Control register */ 29 u32 fr; /* 0x18 Flag register (Read only) */ 30 #ifdef CONFIG_PL011_SERIAL_RLCR 31 u32 pl011_rlcr; /* 0x1c Receive line control register */ 32 #else 33 u32 reserved; 34 #endif 35 u32 ilpr; /* 0x20 IrDA low-power counter register */ 36 u32 pl011_ibrd; /* 0x24 Integer baud rate register */ 37 u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ 38 u32 pl011_lcrh; /* 0x2C Line control register */ 39 u32 pl011_cr; /* 0x30 Control register */ 40 }; 41 #endif 42 43 #define UART_PL01x_RSR_OE 0x08 44 #define UART_PL01x_RSR_BE 0x04 45 #define UART_PL01x_RSR_PE 0x02 46 #define UART_PL01x_RSR_FE 0x01 47 48 #define UART_PL01x_FR_TXFE 0x80 49 #define UART_PL01x_FR_RXFF 0x40 50 #define UART_PL01x_FR_TXFF 0x20 51 #define UART_PL01x_FR_RXFE 0x10 52 #define UART_PL01x_FR_BUSY 0x08 53 #define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) 54 55 /* 56 * PL010 definitions 57 * 58 */ 59 #define UART_PL010_CR_LPE (1 << 7) 60 #define UART_PL010_CR_RTIE (1 << 6) 61 #define UART_PL010_CR_TIE (1 << 5) 62 #define UART_PL010_CR_RIE (1 << 4) 63 #define UART_PL010_CR_MSIE (1 << 3) 64 #define UART_PL010_CR_IIRLP (1 << 2) 65 #define UART_PL010_CR_SIREN (1 << 1) 66 #define UART_PL010_CR_UARTEN (1 << 0) 67 68 #define UART_PL010_LCRH_WLEN_8 (3 << 5) 69 #define UART_PL010_LCRH_WLEN_7 (2 << 5) 70 #define UART_PL010_LCRH_WLEN_6 (1 << 5) 71 #define UART_PL010_LCRH_WLEN_5 (0 << 5) 72 #define UART_PL010_LCRH_FEN (1 << 4) 73 #define UART_PL010_LCRH_STP2 (1 << 3) 74 #define UART_PL010_LCRH_EPS (1 << 2) 75 #define UART_PL010_LCRH_PEN (1 << 1) 76 #define UART_PL010_LCRH_BRK (1 << 0) 77 78 79 #define UART_PL010_BAUD_460800 1 80 #define UART_PL010_BAUD_230400 3 81 #define UART_PL010_BAUD_115200 7 82 #define UART_PL010_BAUD_57600 15 83 #define UART_PL010_BAUD_38400 23 84 #define UART_PL010_BAUD_19200 47 85 #define UART_PL010_BAUD_14400 63 86 #define UART_PL010_BAUD_9600 95 87 #define UART_PL010_BAUD_4800 191 88 #define UART_PL010_BAUD_2400 383 89 #define UART_PL010_BAUD_1200 767 90 /* 91 * PL011 definitions 92 * 93 */ 94 #define UART_PL011_LCRH_SPS (1 << 7) 95 #define UART_PL011_LCRH_WLEN_8 (3 << 5) 96 #define UART_PL011_LCRH_WLEN_7 (2 << 5) 97 #define UART_PL011_LCRH_WLEN_6 (1 << 5) 98 #define UART_PL011_LCRH_WLEN_5 (0 << 5) 99 #define UART_PL011_LCRH_FEN (1 << 4) 100 #define UART_PL011_LCRH_STP2 (1 << 3) 101 #define UART_PL011_LCRH_EPS (1 << 2) 102 #define UART_PL011_LCRH_PEN (1 << 1) 103 #define UART_PL011_LCRH_BRK (1 << 0) 104 105 #define UART_PL011_CR_CTSEN (1 << 15) 106 #define UART_PL011_CR_RTSEN (1 << 14) 107 #define UART_PL011_CR_OUT2 (1 << 13) 108 #define UART_PL011_CR_OUT1 (1 << 12) 109 #define UART_PL011_CR_RTS (1 << 11) 110 #define UART_PL011_CR_DTR (1 << 10) 111 #define UART_PL011_CR_RXE (1 << 9) 112 #define UART_PL011_CR_TXE (1 << 8) 113 #define UART_PL011_CR_LPE (1 << 7) 114 #define UART_PL011_CR_IIRLP (1 << 2) 115 #define UART_PL011_CR_SIREN (1 << 1) 116 #define UART_PL011_CR_UARTEN (1 << 0) 117 118 #define UART_PL011_IMSC_OEIM (1 << 10) 119 #define UART_PL011_IMSC_BEIM (1 << 9) 120 #define UART_PL011_IMSC_PEIM (1 << 8) 121 #define UART_PL011_IMSC_FEIM (1 << 7) 122 #define UART_PL011_IMSC_RTIM (1 << 6) 123 #define UART_PL011_IMSC_TXIM (1 << 5) 124 #define UART_PL011_IMSC_RXIM (1 << 4) 125 #define UART_PL011_IMSC_DSRMIM (1 << 3) 126 #define UART_PL011_IMSC_DCDMIM (1 << 2) 127 #define UART_PL011_IMSC_CTSMIM (1 << 1) 128 #define UART_PL011_IMSC_RIMIM (1 << 0) 129