1aed2fbefSSimon Glass /* 2aed2fbefSSimon Glass * (C) Copyright 2003, 2004 3aed2fbefSSimon Glass * ARM Ltd. 4aed2fbefSSimon Glass * Philippe Robin, <philippe.robin@arm.com> 5aed2fbefSSimon Glass * 6aed2fbefSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 7aed2fbefSSimon Glass */ 8aed2fbefSSimon Glass 9aed2fbefSSimon Glass /* 10aed2fbefSSimon Glass * ARM PrimeCell UART's (PL010 & PL011) 11aed2fbefSSimon Glass * ------------------------------------ 12aed2fbefSSimon Glass * 13aed2fbefSSimon Glass * Definitions common to both PL010 & PL011 14aed2fbefSSimon Glass * 15aed2fbefSSimon Glass */ 16aed2fbefSSimon Glass 17aed2fbefSSimon Glass #ifndef __ASSEMBLY__ 18aed2fbefSSimon Glass /* 19aed2fbefSSimon Glass * We can use a combined structure for PL010 and PL011, because they overlap 20aed2fbefSSimon Glass * only in common registers. 21aed2fbefSSimon Glass */ 22aed2fbefSSimon Glass struct pl01x_regs { 23aed2fbefSSimon Glass u32 dr; /* 0x00 Data register */ 24aed2fbefSSimon Glass u32 ecr; /* 0x04 Error clear register (Write) */ 25aed2fbefSSimon Glass u32 pl010_lcrh; /* 0x08 Line control register, high byte */ 26aed2fbefSSimon Glass u32 pl010_lcrm; /* 0x0C Line control register, middle byte */ 27aed2fbefSSimon Glass u32 pl010_lcrl; /* 0x10 Line control register, low byte */ 28aed2fbefSSimon Glass u32 pl010_cr; /* 0x14 Control register */ 29aed2fbefSSimon Glass u32 fr; /* 0x18 Flag register (Read only) */ 30aed2fbefSSimon Glass #ifdef CONFIG_PL011_SERIAL_RLCR 31aed2fbefSSimon Glass u32 pl011_rlcr; /* 0x1c Receive line control register */ 32aed2fbefSSimon Glass #else 33aed2fbefSSimon Glass u32 reserved; 34aed2fbefSSimon Glass #endif 35aed2fbefSSimon Glass u32 ilpr; /* 0x20 IrDA low-power counter register */ 36aed2fbefSSimon Glass u32 pl011_ibrd; /* 0x24 Integer baud rate register */ 37aed2fbefSSimon Glass u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ 38aed2fbefSSimon Glass u32 pl011_lcrh; /* 0x2C Line control register */ 39aed2fbefSSimon Glass u32 pl011_cr; /* 0x30 Control register */ 40aed2fbefSSimon Glass }; 416001985fSAlexander Graf 426001985fSAlexander Graf #ifdef CONFIG_DM_SERIAL 436001985fSAlexander Graf 446001985fSAlexander Graf int pl01x_serial_ofdata_to_platdata(struct udevice *dev); 456001985fSAlexander Graf int pl01x_serial_probe(struct udevice *dev); 46*c9bf43ddSAlexander Graf 47*c9bf43ddSAlexander Graf /* Needed for external pl01x_serial_ops drivers */ 48*c9bf43ddSAlexander Graf int pl01x_serial_putc(struct udevice *dev, const char ch); 49*c9bf43ddSAlexander Graf int pl01x_serial_pending(struct udevice *dev, bool input); 50*c9bf43ddSAlexander Graf int pl01x_serial_getc(struct udevice *dev); 51*c9bf43ddSAlexander Graf int pl01x_serial_setbrg(struct udevice *dev, int baudrate); 526001985fSAlexander Graf 536001985fSAlexander Graf struct pl01x_priv { 546001985fSAlexander Graf struct pl01x_regs *regs; 556001985fSAlexander Graf enum pl01x_type type; 566001985fSAlexander Graf }; 576001985fSAlexander Graf 586001985fSAlexander Graf #endif /* CONFIG_DM_SERIAL */ 596001985fSAlexander Graf #endif /* !__ASSEMBLY__ */ 60aed2fbefSSimon Glass 61aed2fbefSSimon Glass #define UART_PL01x_RSR_OE 0x08 62aed2fbefSSimon Glass #define UART_PL01x_RSR_BE 0x04 63aed2fbefSSimon Glass #define UART_PL01x_RSR_PE 0x02 64aed2fbefSSimon Glass #define UART_PL01x_RSR_FE 0x01 65aed2fbefSSimon Glass 66aed2fbefSSimon Glass #define UART_PL01x_FR_TXFE 0x80 67aed2fbefSSimon Glass #define UART_PL01x_FR_RXFF 0x40 68aed2fbefSSimon Glass #define UART_PL01x_FR_TXFF 0x20 69aed2fbefSSimon Glass #define UART_PL01x_FR_RXFE 0x10 70aed2fbefSSimon Glass #define UART_PL01x_FR_BUSY 0x08 71aed2fbefSSimon Glass #define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) 72aed2fbefSSimon Glass 73aed2fbefSSimon Glass /* 74aed2fbefSSimon Glass * PL010 definitions 75aed2fbefSSimon Glass * 76aed2fbefSSimon Glass */ 77aed2fbefSSimon Glass #define UART_PL010_CR_LPE (1 << 7) 78aed2fbefSSimon Glass #define UART_PL010_CR_RTIE (1 << 6) 79aed2fbefSSimon Glass #define UART_PL010_CR_TIE (1 << 5) 80aed2fbefSSimon Glass #define UART_PL010_CR_RIE (1 << 4) 81aed2fbefSSimon Glass #define UART_PL010_CR_MSIE (1 << 3) 82aed2fbefSSimon Glass #define UART_PL010_CR_IIRLP (1 << 2) 83aed2fbefSSimon Glass #define UART_PL010_CR_SIREN (1 << 1) 84aed2fbefSSimon Glass #define UART_PL010_CR_UARTEN (1 << 0) 85aed2fbefSSimon Glass 86aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_8 (3 << 5) 87aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_7 (2 << 5) 88aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_6 (1 << 5) 89aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_5 (0 << 5) 90aed2fbefSSimon Glass #define UART_PL010_LCRH_FEN (1 << 4) 91aed2fbefSSimon Glass #define UART_PL010_LCRH_STP2 (1 << 3) 92aed2fbefSSimon Glass #define UART_PL010_LCRH_EPS (1 << 2) 93aed2fbefSSimon Glass #define UART_PL010_LCRH_PEN (1 << 1) 94aed2fbefSSimon Glass #define UART_PL010_LCRH_BRK (1 << 0) 95aed2fbefSSimon Glass 96aed2fbefSSimon Glass 97aed2fbefSSimon Glass #define UART_PL010_BAUD_460800 1 98aed2fbefSSimon Glass #define UART_PL010_BAUD_230400 3 99aed2fbefSSimon Glass #define UART_PL010_BAUD_115200 7 100aed2fbefSSimon Glass #define UART_PL010_BAUD_57600 15 101aed2fbefSSimon Glass #define UART_PL010_BAUD_38400 23 102aed2fbefSSimon Glass #define UART_PL010_BAUD_19200 47 103aed2fbefSSimon Glass #define UART_PL010_BAUD_14400 63 104aed2fbefSSimon Glass #define UART_PL010_BAUD_9600 95 105aed2fbefSSimon Glass #define UART_PL010_BAUD_4800 191 106aed2fbefSSimon Glass #define UART_PL010_BAUD_2400 383 107aed2fbefSSimon Glass #define UART_PL010_BAUD_1200 767 108aed2fbefSSimon Glass /* 109aed2fbefSSimon Glass * PL011 definitions 110aed2fbefSSimon Glass * 111aed2fbefSSimon Glass */ 112aed2fbefSSimon Glass #define UART_PL011_LCRH_SPS (1 << 7) 113aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_8 (3 << 5) 114aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_7 (2 << 5) 115aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_6 (1 << 5) 116aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_5 (0 << 5) 117aed2fbefSSimon Glass #define UART_PL011_LCRH_FEN (1 << 4) 118aed2fbefSSimon Glass #define UART_PL011_LCRH_STP2 (1 << 3) 119aed2fbefSSimon Glass #define UART_PL011_LCRH_EPS (1 << 2) 120aed2fbefSSimon Glass #define UART_PL011_LCRH_PEN (1 << 1) 121aed2fbefSSimon Glass #define UART_PL011_LCRH_BRK (1 << 0) 122aed2fbefSSimon Glass 123aed2fbefSSimon Glass #define UART_PL011_CR_CTSEN (1 << 15) 124aed2fbefSSimon Glass #define UART_PL011_CR_RTSEN (1 << 14) 125aed2fbefSSimon Glass #define UART_PL011_CR_OUT2 (1 << 13) 126aed2fbefSSimon Glass #define UART_PL011_CR_OUT1 (1 << 12) 127aed2fbefSSimon Glass #define UART_PL011_CR_RTS (1 << 11) 128aed2fbefSSimon Glass #define UART_PL011_CR_DTR (1 << 10) 129aed2fbefSSimon Glass #define UART_PL011_CR_RXE (1 << 9) 130aed2fbefSSimon Glass #define UART_PL011_CR_TXE (1 << 8) 131aed2fbefSSimon Glass #define UART_PL011_CR_LPE (1 << 7) 132aed2fbefSSimon Glass #define UART_PL011_CR_IIRLP (1 << 2) 133aed2fbefSSimon Glass #define UART_PL011_CR_SIREN (1 << 1) 134aed2fbefSSimon Glass #define UART_PL011_CR_UARTEN (1 << 0) 135aed2fbefSSimon Glass 136aed2fbefSSimon Glass #define UART_PL011_IMSC_OEIM (1 << 10) 137aed2fbefSSimon Glass #define UART_PL011_IMSC_BEIM (1 << 9) 138aed2fbefSSimon Glass #define UART_PL011_IMSC_PEIM (1 << 8) 139aed2fbefSSimon Glass #define UART_PL011_IMSC_FEIM (1 << 7) 140aed2fbefSSimon Glass #define UART_PL011_IMSC_RTIM (1 << 6) 141aed2fbefSSimon Glass #define UART_PL011_IMSC_TXIM (1 << 5) 142aed2fbefSSimon Glass #define UART_PL011_IMSC_RXIM (1 << 4) 143aed2fbefSSimon Glass #define UART_PL011_IMSC_DSRMIM (1 << 3) 144aed2fbefSSimon Glass #define UART_PL011_IMSC_DCDMIM (1 << 2) 145aed2fbefSSimon Glass #define UART_PL011_IMSC_CTSMIM (1 << 1) 146aed2fbefSSimon Glass #define UART_PL011_IMSC_RIMIM (1 << 0) 147