1*aed2fbefSSimon Glass /* 2*aed2fbefSSimon Glass * (C) Copyright 2003, 2004 3*aed2fbefSSimon Glass * ARM Ltd. 4*aed2fbefSSimon Glass * Philippe Robin, <philippe.robin@arm.com> 5*aed2fbefSSimon Glass * 6*aed2fbefSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 7*aed2fbefSSimon Glass */ 8*aed2fbefSSimon Glass 9*aed2fbefSSimon Glass /* 10*aed2fbefSSimon Glass * ARM PrimeCell UART's (PL010 & PL011) 11*aed2fbefSSimon Glass * ------------------------------------ 12*aed2fbefSSimon Glass * 13*aed2fbefSSimon Glass * Definitions common to both PL010 & PL011 14*aed2fbefSSimon Glass * 15*aed2fbefSSimon Glass */ 16*aed2fbefSSimon Glass 17*aed2fbefSSimon Glass #ifndef __ASSEMBLY__ 18*aed2fbefSSimon Glass /* 19*aed2fbefSSimon Glass * We can use a combined structure for PL010 and PL011, because they overlap 20*aed2fbefSSimon Glass * only in common registers. 21*aed2fbefSSimon Glass */ 22*aed2fbefSSimon Glass struct pl01x_regs { 23*aed2fbefSSimon Glass u32 dr; /* 0x00 Data register */ 24*aed2fbefSSimon Glass u32 ecr; /* 0x04 Error clear register (Write) */ 25*aed2fbefSSimon Glass u32 pl010_lcrh; /* 0x08 Line control register, high byte */ 26*aed2fbefSSimon Glass u32 pl010_lcrm; /* 0x0C Line control register, middle byte */ 27*aed2fbefSSimon Glass u32 pl010_lcrl; /* 0x10 Line control register, low byte */ 28*aed2fbefSSimon Glass u32 pl010_cr; /* 0x14 Control register */ 29*aed2fbefSSimon Glass u32 fr; /* 0x18 Flag register (Read only) */ 30*aed2fbefSSimon Glass #ifdef CONFIG_PL011_SERIAL_RLCR 31*aed2fbefSSimon Glass u32 pl011_rlcr; /* 0x1c Receive line control register */ 32*aed2fbefSSimon Glass #else 33*aed2fbefSSimon Glass u32 reserved; 34*aed2fbefSSimon Glass #endif 35*aed2fbefSSimon Glass u32 ilpr; /* 0x20 IrDA low-power counter register */ 36*aed2fbefSSimon Glass u32 pl011_ibrd; /* 0x24 Integer baud rate register */ 37*aed2fbefSSimon Glass u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ 38*aed2fbefSSimon Glass u32 pl011_lcrh; /* 0x2C Line control register */ 39*aed2fbefSSimon Glass u32 pl011_cr; /* 0x30 Control register */ 40*aed2fbefSSimon Glass }; 41*aed2fbefSSimon Glass #endif 42*aed2fbefSSimon Glass 43*aed2fbefSSimon Glass #define UART_PL01x_RSR_OE 0x08 44*aed2fbefSSimon Glass #define UART_PL01x_RSR_BE 0x04 45*aed2fbefSSimon Glass #define UART_PL01x_RSR_PE 0x02 46*aed2fbefSSimon Glass #define UART_PL01x_RSR_FE 0x01 47*aed2fbefSSimon Glass 48*aed2fbefSSimon Glass #define UART_PL01x_FR_TXFE 0x80 49*aed2fbefSSimon Glass #define UART_PL01x_FR_RXFF 0x40 50*aed2fbefSSimon Glass #define UART_PL01x_FR_TXFF 0x20 51*aed2fbefSSimon Glass #define UART_PL01x_FR_RXFE 0x10 52*aed2fbefSSimon Glass #define UART_PL01x_FR_BUSY 0x08 53*aed2fbefSSimon Glass #define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) 54*aed2fbefSSimon Glass 55*aed2fbefSSimon Glass /* 56*aed2fbefSSimon Glass * PL010 definitions 57*aed2fbefSSimon Glass * 58*aed2fbefSSimon Glass */ 59*aed2fbefSSimon Glass #define UART_PL010_CR_LPE (1 << 7) 60*aed2fbefSSimon Glass #define UART_PL010_CR_RTIE (1 << 6) 61*aed2fbefSSimon Glass #define UART_PL010_CR_TIE (1 << 5) 62*aed2fbefSSimon Glass #define UART_PL010_CR_RIE (1 << 4) 63*aed2fbefSSimon Glass #define UART_PL010_CR_MSIE (1 << 3) 64*aed2fbefSSimon Glass #define UART_PL010_CR_IIRLP (1 << 2) 65*aed2fbefSSimon Glass #define UART_PL010_CR_SIREN (1 << 1) 66*aed2fbefSSimon Glass #define UART_PL010_CR_UARTEN (1 << 0) 67*aed2fbefSSimon Glass 68*aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_8 (3 << 5) 69*aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_7 (2 << 5) 70*aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_6 (1 << 5) 71*aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_5 (0 << 5) 72*aed2fbefSSimon Glass #define UART_PL010_LCRH_FEN (1 << 4) 73*aed2fbefSSimon Glass #define UART_PL010_LCRH_STP2 (1 << 3) 74*aed2fbefSSimon Glass #define UART_PL010_LCRH_EPS (1 << 2) 75*aed2fbefSSimon Glass #define UART_PL010_LCRH_PEN (1 << 1) 76*aed2fbefSSimon Glass #define UART_PL010_LCRH_BRK (1 << 0) 77*aed2fbefSSimon Glass 78*aed2fbefSSimon Glass 79*aed2fbefSSimon Glass #define UART_PL010_BAUD_460800 1 80*aed2fbefSSimon Glass #define UART_PL010_BAUD_230400 3 81*aed2fbefSSimon Glass #define UART_PL010_BAUD_115200 7 82*aed2fbefSSimon Glass #define UART_PL010_BAUD_57600 15 83*aed2fbefSSimon Glass #define UART_PL010_BAUD_38400 23 84*aed2fbefSSimon Glass #define UART_PL010_BAUD_19200 47 85*aed2fbefSSimon Glass #define UART_PL010_BAUD_14400 63 86*aed2fbefSSimon Glass #define UART_PL010_BAUD_9600 95 87*aed2fbefSSimon Glass #define UART_PL010_BAUD_4800 191 88*aed2fbefSSimon Glass #define UART_PL010_BAUD_2400 383 89*aed2fbefSSimon Glass #define UART_PL010_BAUD_1200 767 90*aed2fbefSSimon Glass /* 91*aed2fbefSSimon Glass * PL011 definitions 92*aed2fbefSSimon Glass * 93*aed2fbefSSimon Glass */ 94*aed2fbefSSimon Glass #define UART_PL011_LCRH_SPS (1 << 7) 95*aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_8 (3 << 5) 96*aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_7 (2 << 5) 97*aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_6 (1 << 5) 98*aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_5 (0 << 5) 99*aed2fbefSSimon Glass #define UART_PL011_LCRH_FEN (1 << 4) 100*aed2fbefSSimon Glass #define UART_PL011_LCRH_STP2 (1 << 3) 101*aed2fbefSSimon Glass #define UART_PL011_LCRH_EPS (1 << 2) 102*aed2fbefSSimon Glass #define UART_PL011_LCRH_PEN (1 << 1) 103*aed2fbefSSimon Glass #define UART_PL011_LCRH_BRK (1 << 0) 104*aed2fbefSSimon Glass 105*aed2fbefSSimon Glass #define UART_PL011_CR_CTSEN (1 << 15) 106*aed2fbefSSimon Glass #define UART_PL011_CR_RTSEN (1 << 14) 107*aed2fbefSSimon Glass #define UART_PL011_CR_OUT2 (1 << 13) 108*aed2fbefSSimon Glass #define UART_PL011_CR_OUT1 (1 << 12) 109*aed2fbefSSimon Glass #define UART_PL011_CR_RTS (1 << 11) 110*aed2fbefSSimon Glass #define UART_PL011_CR_DTR (1 << 10) 111*aed2fbefSSimon Glass #define UART_PL011_CR_RXE (1 << 9) 112*aed2fbefSSimon Glass #define UART_PL011_CR_TXE (1 << 8) 113*aed2fbefSSimon Glass #define UART_PL011_CR_LPE (1 << 7) 114*aed2fbefSSimon Glass #define UART_PL011_CR_IIRLP (1 << 2) 115*aed2fbefSSimon Glass #define UART_PL011_CR_SIREN (1 << 1) 116*aed2fbefSSimon Glass #define UART_PL011_CR_UARTEN (1 << 0) 117*aed2fbefSSimon Glass 118*aed2fbefSSimon Glass #define UART_PL011_IMSC_OEIM (1 << 10) 119*aed2fbefSSimon Glass #define UART_PL011_IMSC_BEIM (1 << 9) 120*aed2fbefSSimon Glass #define UART_PL011_IMSC_PEIM (1 << 8) 121*aed2fbefSSimon Glass #define UART_PL011_IMSC_FEIM (1 << 7) 122*aed2fbefSSimon Glass #define UART_PL011_IMSC_RTIM (1 << 6) 123*aed2fbefSSimon Glass #define UART_PL011_IMSC_TXIM (1 << 5) 124*aed2fbefSSimon Glass #define UART_PL011_IMSC_RXIM (1 << 4) 125*aed2fbefSSimon Glass #define UART_PL011_IMSC_DSRMIM (1 << 3) 126*aed2fbefSSimon Glass #define UART_PL011_IMSC_DCDMIM (1 << 2) 127*aed2fbefSSimon Glass #define UART_PL011_IMSC_CTSMIM (1 << 1) 128*aed2fbefSSimon Glass #define UART_PL011_IMSC_RIMIM (1 << 0) 129