1 /*
2  * (C) Copyright 2000
3  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4  *
5  * (C) Copyright 2004
6  * ARM Ltd.
7  * Philippe Robin, <philippe.robin@arm.com>
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
29 
30 #include <common.h>
31 #include <watchdog.h>
32 #include <asm/io.h>
33 #include <serial.h>
34 #include <linux/compiler.h>
35 #include "serial_pl01x.h"
36 
37 /*
38  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
39  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
40  * Versatile PB has four UARTs.
41  */
42 #define CONSOLE_PORT CONFIG_CONS_INDEX
43 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
44 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
45 
46 static void pl01x_putc (int portnum, char c);
47 static int pl01x_getc (int portnum);
48 static int pl01x_tstc (int portnum);
49 unsigned int baudrate = CONFIG_BAUDRATE;
50 DECLARE_GLOBAL_DATA_PTR;
51 
52 static struct pl01x_regs *pl01x_get_regs(int portnum)
53 {
54 	return (struct pl01x_regs *) port[portnum];
55 }
56 
57 #ifdef CONFIG_PL010_SERIAL
58 
59 static int pl01x_serial_init(void)
60 {
61 	struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
62 	unsigned int divisor;
63 
64 	/* First, disable everything */
65 	writel(0, &regs->pl010_cr);
66 
67 	/* Set baud rate */
68 	switch (baudrate) {
69 	case 9600:
70 		divisor = UART_PL010_BAUD_9600;
71 		break;
72 
73 	case 19200:
74 		divisor = UART_PL010_BAUD_9600;
75 		break;
76 
77 	case 38400:
78 		divisor = UART_PL010_BAUD_38400;
79 		break;
80 
81 	case 57600:
82 		divisor = UART_PL010_BAUD_57600;
83 		break;
84 
85 	case 115200:
86 		divisor = UART_PL010_BAUD_115200;
87 		break;
88 
89 	default:
90 		divisor = UART_PL010_BAUD_38400;
91 	}
92 
93 	writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
94 	writel(divisor & 0xff, &regs->pl010_lcrl);
95 
96 	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
97 	writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);
98 
99 	/* Finally, enable the UART */
100 	writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
101 
102 	return 0;
103 }
104 
105 #endif /* CONFIG_PL010_SERIAL */
106 
107 #ifdef CONFIG_PL011_SERIAL
108 
109 static int pl01x_serial_init(void)
110 {
111 	struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
112 	unsigned int temp;
113 	unsigned int divider;
114 	unsigned int remainder;
115 	unsigned int fraction;
116 	unsigned int lcr;
117 
118 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
119 	/* Empty RX fifo if necessary */
120 	if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
121 		while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
122 			readl(&regs->dr);
123 	}
124 #endif
125 
126 	/* First, disable everything */
127 	writel(0, &regs->pl011_cr);
128 
129 	/*
130 	 * Set baud rate
131 	 *
132 	 * IBRD = UART_CLK / (16 * BAUD_RATE)
133 	 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
134 	 */
135 	temp = 16 * baudrate;
136 	divider = CONFIG_PL011_CLOCK / temp;
137 	remainder = CONFIG_PL011_CLOCK % temp;
138 	temp = (8 * remainder) / baudrate;
139 	fraction = (temp >> 1) + (temp & 1);
140 
141 	writel(divider, &regs->pl011_ibrd);
142 	writel(fraction, &regs->pl011_fbrd);
143 
144 	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
145 	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
146 	writel(lcr, &regs->pl011_lcrh);
147 
148 #ifdef CONFIG_PL011_SERIAL_RLCR
149 	{
150 		int i;
151 
152 		/*
153 		 * Program receive line control register after waiting
154 		 * 10 bus cycles.  Delay be writing to readonly register
155 		 * 10 times
156 		 */
157 		for (i = 0; i < 10; i++)
158 			writel(lcr, &regs->fr);
159 
160 		writel(lcr, &regs->pl011_rlcr);
161 		/* lcrh needs to be set again for change to be effective */
162 		writel(lcr, &regs->pl011_lcrh);
163 	}
164 #endif
165 	/* Finally, enable the UART */
166 	writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
167 	       &regs->pl011_cr);
168 
169 	return 0;
170 }
171 
172 #endif /* CONFIG_PL011_SERIAL */
173 
174 static void pl01x_serial_putc(const char c)
175 {
176 	if (c == '\n')
177 		pl01x_putc (CONSOLE_PORT, '\r');
178 
179 	pl01x_putc (CONSOLE_PORT, c);
180 }
181 
182 static int pl01x_serial_getc(void)
183 {
184 	return pl01x_getc (CONSOLE_PORT);
185 }
186 
187 static int pl01x_serial_tstc(void)
188 {
189 	return pl01x_tstc (CONSOLE_PORT);
190 }
191 
192 static void pl01x_serial_setbrg(void)
193 {
194 	struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
195 
196 	baudrate = gd->baudrate;
197 	/*
198 	 * Flush FIFO and wait for non-busy before changing baudrate to avoid
199 	 * crap in console
200 	 */
201 	while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
202 		WATCHDOG_RESET();
203 	while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
204 		WATCHDOG_RESET();
205 	serial_init();
206 }
207 
208 static void pl01x_putc (int portnum, char c)
209 {
210 	struct pl01x_regs *regs = pl01x_get_regs(portnum);
211 
212 	/* Wait until there is space in the FIFO */
213 	while (readl(&regs->fr) & UART_PL01x_FR_TXFF)
214 		WATCHDOG_RESET();
215 
216 	/* Send the character */
217 	writel(c, &regs->dr);
218 }
219 
220 static int pl01x_getc (int portnum)
221 {
222 	struct pl01x_regs *regs = pl01x_get_regs(portnum);
223 	unsigned int data;
224 
225 	/* Wait until there is data in the FIFO */
226 	while (readl(&regs->fr) & UART_PL01x_FR_RXFE)
227 		WATCHDOG_RESET();
228 
229 	data = readl(&regs->dr);
230 
231 	/* Check for an error flag */
232 	if (data & 0xFFFFFF00) {
233 		/* Clear the error */
234 		writel(0xFFFFFFFF, &regs->ecr);
235 		return -1;
236 	}
237 
238 	return (int) data;
239 }
240 
241 static int pl01x_tstc (int portnum)
242 {
243 	struct pl01x_regs *regs = pl01x_get_regs(portnum);
244 
245 	WATCHDOG_RESET();
246 	return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
247 }
248 
249 static struct serial_device pl01x_serial_drv = {
250 	.name	= "pl01x_serial",
251 	.start	= pl01x_serial_init,
252 	.stop	= NULL,
253 	.setbrg	= pl01x_serial_setbrg,
254 	.putc	= pl01x_serial_putc,
255 	.puts	= default_serial_puts,
256 	.getc	= pl01x_serial_getc,
257 	.tstc	= pl01x_serial_tstc,
258 };
259 
260 void pl01x_serial_initialize(void)
261 {
262 	serial_register(&pl01x_serial_drv);
263 }
264 
265 __weak struct serial_device *default_serial_console(void)
266 {
267 	return &pl01x_serial_drv;
268 }
269