1 /* 2 * (C) Copyright 2000 3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 4 * 5 * (C) Copyright 2004 6 * ARM Ltd. 7 * Philippe Robin, <philippe.robin@arm.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ 13 14 #include <common.h> 15 #include <watchdog.h> 16 #include <asm/io.h> 17 #include <serial.h> 18 #include <linux/compiler.h> 19 #include "serial_pl01x.h" 20 21 /* 22 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 23 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 24 * Versatile PB has four UARTs. 25 */ 26 #define CONSOLE_PORT CONFIG_CONS_INDEX 27 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; 28 #define NUM_PORTS (sizeof(port)/sizeof(port[0])) 29 30 static void pl01x_putc (int portnum, char c); 31 static int pl01x_getc (int portnum); 32 static int pl01x_tstc (int portnum); 33 unsigned int baudrate = CONFIG_BAUDRATE; 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static struct pl01x_regs *pl01x_get_regs(int portnum) 37 { 38 return (struct pl01x_regs *) port[portnum]; 39 } 40 41 #ifdef CONFIG_PL010_SERIAL 42 43 static int pl01x_serial_init(void) 44 { 45 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); 46 unsigned int divisor; 47 48 /* First, disable everything */ 49 writel(0, ®s->pl010_cr); 50 51 /* Set baud rate */ 52 switch (baudrate) { 53 case 9600: 54 divisor = UART_PL010_BAUD_9600; 55 break; 56 57 case 19200: 58 divisor = UART_PL010_BAUD_9600; 59 break; 60 61 case 38400: 62 divisor = UART_PL010_BAUD_38400; 63 break; 64 65 case 57600: 66 divisor = UART_PL010_BAUD_57600; 67 break; 68 69 case 115200: 70 divisor = UART_PL010_BAUD_115200; 71 break; 72 73 default: 74 divisor = UART_PL010_BAUD_38400; 75 } 76 77 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); 78 writel(divisor & 0xff, ®s->pl010_lcrl); 79 80 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ 81 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh); 82 83 /* Finally, enable the UART */ 84 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); 85 86 return 0; 87 } 88 89 #endif /* CONFIG_PL010_SERIAL */ 90 91 #ifdef CONFIG_PL011_SERIAL 92 93 static int pl01x_serial_init(void) 94 { 95 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); 96 unsigned int temp; 97 unsigned int divider; 98 unsigned int remainder; 99 unsigned int fraction; 100 unsigned int lcr; 101 102 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT 103 /* Empty RX fifo if necessary */ 104 if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { 105 while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) 106 readl(®s->dr); 107 } 108 #endif 109 110 /* First, disable everything */ 111 writel(0, ®s->pl011_cr); 112 113 /* 114 * Set baud rate 115 * 116 * IBRD = UART_CLK / (16 * BAUD_RATE) 117 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) 118 */ 119 temp = 16 * baudrate; 120 divider = CONFIG_PL011_CLOCK / temp; 121 remainder = CONFIG_PL011_CLOCK % temp; 122 temp = (8 * remainder) / baudrate; 123 fraction = (temp >> 1) + (temp & 1); 124 125 writel(divider, ®s->pl011_ibrd); 126 writel(fraction, ®s->pl011_fbrd); 127 128 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ 129 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; 130 writel(lcr, ®s->pl011_lcrh); 131 132 #ifdef CONFIG_PL011_SERIAL_RLCR 133 { 134 int i; 135 136 /* 137 * Program receive line control register after waiting 138 * 10 bus cycles. Delay be writing to readonly register 139 * 10 times 140 */ 141 for (i = 0; i < 10; i++) 142 writel(lcr, ®s->fr); 143 144 writel(lcr, ®s->pl011_rlcr); 145 /* lcrh needs to be set again for change to be effective */ 146 writel(lcr, ®s->pl011_lcrh); 147 } 148 #endif 149 /* Finally, enable the UART */ 150 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE | 151 UART_PL011_CR_RTS, ®s->pl011_cr); 152 153 return 0; 154 } 155 156 #endif /* CONFIG_PL011_SERIAL */ 157 158 static void pl01x_serial_putc(const char c) 159 { 160 if (c == '\n') 161 pl01x_putc (CONSOLE_PORT, '\r'); 162 163 pl01x_putc (CONSOLE_PORT, c); 164 } 165 166 static int pl01x_serial_getc(void) 167 { 168 return pl01x_getc (CONSOLE_PORT); 169 } 170 171 static int pl01x_serial_tstc(void) 172 { 173 return pl01x_tstc (CONSOLE_PORT); 174 } 175 176 static void pl01x_serial_setbrg(void) 177 { 178 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); 179 180 baudrate = gd->baudrate; 181 /* 182 * Flush FIFO and wait for non-busy before changing baudrate to avoid 183 * crap in console 184 */ 185 while (!(readl(®s->fr) & UART_PL01x_FR_TXFE)) 186 WATCHDOG_RESET(); 187 while (readl(®s->fr) & UART_PL01x_FR_BUSY) 188 WATCHDOG_RESET(); 189 serial_init(); 190 } 191 192 static void pl01x_putc (int portnum, char c) 193 { 194 struct pl01x_regs *regs = pl01x_get_regs(portnum); 195 196 /* Wait until there is space in the FIFO */ 197 while (readl(®s->fr) & UART_PL01x_FR_TXFF) 198 WATCHDOG_RESET(); 199 200 /* Send the character */ 201 writel(c, ®s->dr); 202 } 203 204 static int pl01x_getc (int portnum) 205 { 206 struct pl01x_regs *regs = pl01x_get_regs(portnum); 207 unsigned int data; 208 209 /* Wait until there is data in the FIFO */ 210 while (readl(®s->fr) & UART_PL01x_FR_RXFE) 211 WATCHDOG_RESET(); 212 213 data = readl(®s->dr); 214 215 /* Check for an error flag */ 216 if (data & 0xFFFFFF00) { 217 /* Clear the error */ 218 writel(0xFFFFFFFF, ®s->ecr); 219 return -1; 220 } 221 222 return (int) data; 223 } 224 225 static int pl01x_tstc (int portnum) 226 { 227 struct pl01x_regs *regs = pl01x_get_regs(portnum); 228 229 WATCHDOG_RESET(); 230 return !(readl(®s->fr) & UART_PL01x_FR_RXFE); 231 } 232 233 static struct serial_device pl01x_serial_drv = { 234 .name = "pl01x_serial", 235 .start = pl01x_serial_init, 236 .stop = NULL, 237 .setbrg = pl01x_serial_setbrg, 238 .putc = pl01x_serial_putc, 239 .puts = default_serial_puts, 240 .getc = pl01x_serial_getc, 241 .tstc = pl01x_serial_tstc, 242 }; 243 244 void pl01x_serial_initialize(void) 245 { 246 serial_register(&pl01x_serial_drv); 247 } 248 249 __weak struct serial_device *default_serial_console(void) 250 { 251 return &pl01x_serial_drv; 252 } 253