1 /*
2  * (C) Copyright 2000
3  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4  *
5  * (C) Copyright 2004
6  * ARM Ltd.
7  * Philippe Robin, <philippe.robin@arm.com>
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
13 
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <watchdog.h>
18 #include <asm/io.h>
19 #include <serial.h>
20 #include <dm/platform_data/serial_pl01x.h>
21 #include <linux/compiler.h>
22 #include "serial_pl01x_internal.h"
23 
24 #ifndef CONFIG_DM_SERIAL
25 
26 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
27 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
28 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
29 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 #endif
33 
34 static int pl01x_putc(struct pl01x_regs *regs, char c)
35 {
36 	/* Wait until there is space in the FIFO */
37 	if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
38 		return -EAGAIN;
39 
40 	/* Send the character */
41 	writel(c, &regs->dr);
42 
43 	return 0;
44 }
45 
46 static int pl01x_getc(struct pl01x_regs *regs)
47 {
48 	unsigned int data;
49 
50 	/* Wait until there is data in the FIFO */
51 	if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
52 		return -EAGAIN;
53 
54 	data = readl(&regs->dr);
55 
56 	/* Check for an error flag */
57 	if (data & 0xFFFFFF00) {
58 		/* Clear the error */
59 		writel(0xFFFFFFFF, &regs->ecr);
60 		return -1;
61 	}
62 
63 	return (int) data;
64 }
65 
66 static int pl01x_tstc(struct pl01x_regs *regs)
67 {
68 	WATCHDOG_RESET();
69 	return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
70 }
71 
72 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
73 				     enum pl01x_type type)
74 {
75 	switch (type) {
76 	case TYPE_PL010:
77 		/* disable everything */
78 		writel(0, &regs->pl010_cr);
79 		break;
80 	case TYPE_PL011:
81 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
82 		/* Empty RX fifo if necessary */
83 		if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
84 			while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
85 				readl(&regs->dr);
86 		}
87 #endif
88 		/* disable everything */
89 		writel(0, &regs->pl011_cr);
90 		break;
91 	default:
92 		return -EINVAL;
93 	}
94 
95 	return 0;
96 }
97 
98 static int set_line_control(struct pl01x_regs *regs)
99 {
100 	unsigned int lcr;
101 	/*
102 	 * Internal update of baud rate register require line
103 	 * control register write
104 	 */
105 	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
106 #ifdef CONFIG_PL011_SERIAL_RLCR
107 	{
108 		int i;
109 
110 		/*
111 		 * Program receive line control register after waiting
112 		 * 10 bus cycles.  Delay be writing to readonly register
113 		 * 10 times
114 		 */
115 		for (i = 0; i < 10; i++)
116 			writel(lcr, &regs->fr);
117 
118 		writel(lcr, &regs->pl011_rlcr);
119 	}
120 #endif
121 	writel(lcr, &regs->pl011_lcrh);
122 	return 0;
123 }
124 
125 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
126 				int clock, int baudrate)
127 {
128 	switch (type) {
129 	case TYPE_PL010: {
130 		unsigned int divisor;
131 
132 		switch (baudrate) {
133 		case 9600:
134 			divisor = UART_PL010_BAUD_9600;
135 			break;
136 		case 19200:
137 			divisor = UART_PL010_BAUD_9600;
138 			break;
139 		case 38400:
140 			divisor = UART_PL010_BAUD_38400;
141 			break;
142 		case 57600:
143 			divisor = UART_PL010_BAUD_57600;
144 			break;
145 		case 115200:
146 			divisor = UART_PL010_BAUD_115200;
147 			break;
148 		default:
149 			divisor = UART_PL010_BAUD_38400;
150 		}
151 
152 		writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
153 		writel(divisor & 0xff, &regs->pl010_lcrl);
154 
155 		/* Finally, enable the UART */
156 		writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
157 		break;
158 	}
159 	case TYPE_PL011: {
160 		unsigned int temp;
161 		unsigned int divider;
162 		unsigned int remainder;
163 		unsigned int fraction;
164 
165 		/*
166 		* Set baud rate
167 		*
168 		* IBRD = UART_CLK / (16 * BAUD_RATE)
169 		* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
170 		*		/ (16 * BAUD_RATE))
171 		*/
172 		temp = 16 * baudrate;
173 		divider = clock / temp;
174 		remainder = clock % temp;
175 		temp = (8 * remainder) / baudrate;
176 		fraction = (temp >> 1) + (temp & 1);
177 
178 		writel(divider, &regs->pl011_ibrd);
179 		writel(fraction, &regs->pl011_fbrd);
180 
181 		set_line_control(regs);
182 		/* Finally, enable the UART */
183 		writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
184 		       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
185 		break;
186 	}
187 	default:
188 		return -EINVAL;
189 	}
190 
191 	return 0;
192 }
193 
194 #ifndef CONFIG_DM_SERIAL
195 static void pl01x_serial_init_baud(int baudrate)
196 {
197 	int clock = 0;
198 
199 #if defined(CONFIG_PL010_SERIAL)
200 	pl01x_type = TYPE_PL010;
201 #elif defined(CONFIG_PL011_SERIAL)
202 	pl01x_type = TYPE_PL011;
203 	clock = CONFIG_PL011_CLOCK;
204 #endif
205 	base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
206 
207 	pl01x_generic_serial_init(base_regs, pl01x_type);
208 	pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
209 }
210 
211 /*
212  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
213  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
214  * Versatile PB has four UARTs.
215  */
216 int pl01x_serial_init(void)
217 {
218 	pl01x_serial_init_baud(CONFIG_BAUDRATE);
219 
220 	return 0;
221 }
222 
223 static void pl01x_serial_putc(const char c)
224 {
225 	if (c == '\n')
226 		while (pl01x_putc(base_regs, '\r') == -EAGAIN);
227 
228 	while (pl01x_putc(base_regs, c) == -EAGAIN);
229 }
230 
231 static int pl01x_serial_getc(void)
232 {
233 	while (1) {
234 		int ch = pl01x_getc(base_regs);
235 
236 		if (ch == -EAGAIN) {
237 			WATCHDOG_RESET();
238 			continue;
239 		}
240 
241 		return ch;
242 	}
243 }
244 
245 static int pl01x_serial_tstc(void)
246 {
247 	return pl01x_tstc(base_regs);
248 }
249 
250 static void pl01x_serial_setbrg(void)
251 {
252 	/*
253 	 * Flush FIFO and wait for non-busy before changing baudrate to avoid
254 	 * crap in console
255 	 */
256 	while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
257 		WATCHDOG_RESET();
258 	while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
259 		WATCHDOG_RESET();
260 	pl01x_serial_init_baud(gd->baudrate);
261 }
262 
263 static struct serial_device pl01x_serial_drv = {
264 	.name	= "pl01x_serial",
265 	.start	= pl01x_serial_init,
266 	.stop	= NULL,
267 	.setbrg	= pl01x_serial_setbrg,
268 	.putc	= pl01x_serial_putc,
269 	.puts	= default_serial_puts,
270 	.getc	= pl01x_serial_getc,
271 	.tstc	= pl01x_serial_tstc,
272 };
273 
274 void pl01x_serial_initialize(void)
275 {
276 	serial_register(&pl01x_serial_drv);
277 }
278 
279 __weak struct serial_device *default_serial_console(void)
280 {
281 	return &pl01x_serial_drv;
282 }
283 
284 #endif /* nCONFIG_DM_SERIAL */
285 
286 #ifdef CONFIG_DM_SERIAL
287 
288 struct pl01x_priv {
289 	struct pl01x_regs *regs;
290 	enum pl01x_type type;
291 };
292 
293 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
294 {
295 	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
296 	struct pl01x_priv *priv = dev_get_priv(dev);
297 
298 	pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
299 
300 	return 0;
301 }
302 
303 static int pl01x_serial_probe(struct udevice *dev)
304 {
305 	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
306 	struct pl01x_priv *priv = dev_get_priv(dev);
307 
308 	priv->regs = (struct pl01x_regs *)plat->base;
309 	priv->type = plat->type;
310 	return pl01x_generic_serial_init(priv->regs, priv->type);
311 }
312 
313 static int pl01x_serial_getc(struct udevice *dev)
314 {
315 	struct pl01x_priv *priv = dev_get_priv(dev);
316 
317 	return pl01x_getc(priv->regs);
318 }
319 
320 static int pl01x_serial_putc(struct udevice *dev, const char ch)
321 {
322 	struct pl01x_priv *priv = dev_get_priv(dev);
323 
324 	return pl01x_putc(priv->regs, ch);
325 }
326 
327 static int pl01x_serial_pending(struct udevice *dev, bool input)
328 {
329 	struct pl01x_priv *priv = dev_get_priv(dev);
330 	unsigned int fr = readl(&priv->regs->fr);
331 
332 	if (input)
333 		return pl01x_tstc(priv->regs);
334 	else
335 		return fr & UART_PL01x_FR_TXFF ? 0 : 1;
336 }
337 
338 static const struct dm_serial_ops pl01x_serial_ops = {
339 	.putc = pl01x_serial_putc,
340 	.pending = pl01x_serial_pending,
341 	.getc = pl01x_serial_getc,
342 	.setbrg = pl01x_serial_setbrg,
343 };
344 
345 U_BOOT_DRIVER(serial_pl01x) = {
346 	.name	= "serial_pl01x",
347 	.id	= UCLASS_SERIAL,
348 	.probe = pl01x_serial_probe,
349 	.ops	= &pl01x_serial_ops,
350 	.flags = DM_FLAG_PRE_RELOC,
351 	.priv_auto_alloc_size = sizeof(struct pl01x_priv),
352 };
353 
354 #endif
355