1 /* 2 * (C) Copyright 2000 3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 4 * 5 * (C) Copyright 2004 6 * ARM Ltd. 7 * Philippe Robin, <philippe.robin@arm.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ 29 30 #include <common.h> 31 #include <watchdog.h> 32 #include <asm/io.h> 33 #include "serial_pl01x.h" 34 35 /* 36 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 37 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 38 * Versatile PB has four UARTs. 39 */ 40 #define CONSOLE_PORT CONFIG_CONS_INDEX 41 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; 42 #define NUM_PORTS (sizeof(port)/sizeof(port[0])) 43 44 static void pl01x_putc (int portnum, char c); 45 static int pl01x_getc (int portnum); 46 static int pl01x_tstc (int portnum); 47 unsigned int baudrate = CONFIG_BAUDRATE; 48 DECLARE_GLOBAL_DATA_PTR; 49 50 static struct pl01x_regs *pl01x_get_regs(int portnum) 51 { 52 return (struct pl01x_regs *) port[portnum]; 53 } 54 55 #ifdef CONFIG_PL010_SERIAL 56 57 int serial_init (void) 58 { 59 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); 60 unsigned int divisor; 61 62 /* First, disable everything */ 63 writel(0, ®s->pl010_cr); 64 65 /* Set baud rate */ 66 switch (baudrate) { 67 case 9600: 68 divisor = UART_PL010_BAUD_9600; 69 break; 70 71 case 19200: 72 divisor = UART_PL010_BAUD_9600; 73 break; 74 75 case 38400: 76 divisor = UART_PL010_BAUD_38400; 77 break; 78 79 case 57600: 80 divisor = UART_PL010_BAUD_57600; 81 break; 82 83 case 115200: 84 divisor = UART_PL010_BAUD_115200; 85 break; 86 87 default: 88 divisor = UART_PL010_BAUD_38400; 89 } 90 91 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); 92 writel(divisor & 0xff, ®s->pl010_lcrl); 93 94 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ 95 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh); 96 97 /* Finally, enable the UART */ 98 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); 99 100 return 0; 101 } 102 103 #endif /* CONFIG_PL010_SERIAL */ 104 105 #ifdef CONFIG_PL011_SERIAL 106 107 int serial_init (void) 108 { 109 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); 110 unsigned int temp; 111 unsigned int divider; 112 unsigned int remainder; 113 unsigned int fraction; 114 unsigned int lcr; 115 116 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT 117 /* Empty RX fifo if necessary */ 118 if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { 119 while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) 120 readl(®s->dr); 121 } 122 #endif 123 124 /* First, disable everything */ 125 writel(0, ®s->pl011_cr); 126 127 /* 128 * Set baud rate 129 * 130 * IBRD = UART_CLK / (16 * BAUD_RATE) 131 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) 132 */ 133 temp = 16 * baudrate; 134 divider = CONFIG_PL011_CLOCK / temp; 135 remainder = CONFIG_PL011_CLOCK % temp; 136 temp = (8 * remainder) / baudrate; 137 fraction = (temp >> 1) + (temp & 1); 138 139 writel(divider, ®s->pl011_ibrd); 140 writel(fraction, ®s->pl011_fbrd); 141 142 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ 143 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; 144 writel(lcr, ®s->pl011_lcrh); 145 146 #ifdef CONFIG_PL011_SERIAL_RLCR 147 { 148 int i; 149 150 /* 151 * Program receive line control register after waiting 152 * 10 bus cycles. Delay be writing to readonly register 153 * 10 times 154 */ 155 for (i = 0; i < 10; i++) 156 writel(lcr, ®s->fr); 157 158 writel(lcr, ®s->pl011_rlcr); 159 } 160 #endif 161 /* Finally, enable the UART */ 162 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, 163 ®s->pl011_cr); 164 165 return 0; 166 } 167 168 #endif /* CONFIG_PL011_SERIAL */ 169 170 void serial_putc (const char c) 171 { 172 if (c == '\n') 173 pl01x_putc (CONSOLE_PORT, '\r'); 174 175 pl01x_putc (CONSOLE_PORT, c); 176 } 177 178 void serial_puts (const char *s) 179 { 180 while (*s) { 181 serial_putc (*s++); 182 } 183 } 184 185 int serial_getc (void) 186 { 187 return pl01x_getc (CONSOLE_PORT); 188 } 189 190 int serial_tstc (void) 191 { 192 return pl01x_tstc (CONSOLE_PORT); 193 } 194 195 void serial_setbrg (void) 196 { 197 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); 198 199 baudrate = gd->baudrate; 200 /* 201 * Flush FIFO and wait for non-busy before changing baudrate to avoid 202 * crap in console 203 */ 204 while (!(readl(®s->fr) & UART_PL01x_FR_TXFE)) 205 WATCHDOG_RESET(); 206 while (readl(®s->fr) & UART_PL01x_FR_BUSY) 207 WATCHDOG_RESET(); 208 serial_init(); 209 } 210 211 static void pl01x_putc (int portnum, char c) 212 { 213 struct pl01x_regs *regs = pl01x_get_regs(portnum); 214 215 /* Wait until there is space in the FIFO */ 216 while (readl(®s->fr) & UART_PL01x_FR_TXFF) 217 WATCHDOG_RESET(); 218 219 /* Send the character */ 220 writel(c, ®s->dr); 221 } 222 223 static int pl01x_getc (int portnum) 224 { 225 struct pl01x_regs *regs = pl01x_get_regs(portnum); 226 unsigned int data; 227 228 /* Wait until there is data in the FIFO */ 229 while (readl(®s->fr) & UART_PL01x_FR_RXFE) 230 WATCHDOG_RESET(); 231 232 data = readl(®s->dr); 233 234 /* Check for an error flag */ 235 if (data & 0xFFFFFF00) { 236 /* Clear the error */ 237 writel(0xFFFFFFFF, ®s->ecr); 238 return -1; 239 } 240 241 return (int) data; 242 } 243 244 static int pl01x_tstc (int portnum) 245 { 246 struct pl01x_regs *regs = pl01x_get_regs(portnum); 247 248 WATCHDOG_RESET(); 249 return !(readl(®s->fr) & UART_PL01x_FR_RXFE); 250 } 251