1 /*
2  * (C) Copyright 2000
3  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4  *
5  * (C) Copyright 2004
6  * ARM Ltd.
7  * Philippe Robin, <philippe.robin@arm.com>
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
29 
30 #include <common.h>
31 #include <watchdog.h>
32 #include <asm/io.h>
33 #include "serial_pl01x.h"
34 
35 /*
36  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
37  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
38  * Versatile PB has four UARTs.
39  */
40 #define CONSOLE_PORT CONFIG_CONS_INDEX
41 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
42 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
43 
44 static void pl01x_putc (int portnum, char c);
45 static int pl01x_getc (int portnum);
46 static int pl01x_tstc (int portnum);
47 unsigned int baudrate = CONFIG_BAUDRATE;
48 DECLARE_GLOBAL_DATA_PTR;
49 
50 #ifdef CONFIG_PL010_SERIAL
51 
52 int serial_init (void)
53 {
54 	unsigned int divisor;
55 
56 	/* First, disable everything */
57 	writel(0x0, port[CONSOLE_PORT] + UART_PL010_CR);
58 
59 	/* Set baud rate */
60 	switch (baudrate) {
61 	case 9600:
62 		divisor = UART_PL010_BAUD_9600;
63 		break;
64 
65 	case 19200:
66 		divisor = UART_PL010_BAUD_9600;
67 		break;
68 
69 	case 38400:
70 		divisor = UART_PL010_BAUD_38400;
71 		break;
72 
73 	case 57600:
74 		divisor = UART_PL010_BAUD_57600;
75 		break;
76 
77 	case 115200:
78 		divisor = UART_PL010_BAUD_115200;
79 		break;
80 
81 	default:
82 		divisor = UART_PL010_BAUD_38400;
83 	}
84 
85 	writel(((divisor & 0xf00) >> 8), port[CONSOLE_PORT] + UART_PL010_LCRM);
86 	writel((divisor & 0xff), port[CONSOLE_PORT] + UART_PL010_LCRL);
87 
88 	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
89 	writel((UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN),
90 		port[CONSOLE_PORT] + UART_PL010_LCRH);
91 
92 	/* Finally, enable the UART */
93 	writel((UART_PL010_CR_UARTEN), port[CONSOLE_PORT] + UART_PL010_CR);
94 
95 	return 0;
96 }
97 
98 #endif /* CONFIG_PL010_SERIAL */
99 
100 #ifdef CONFIG_PL011_SERIAL
101 
102 int serial_init (void)
103 {
104 	unsigned int temp;
105 	unsigned int divider;
106 	unsigned int remainder;
107 	unsigned int fraction;
108 
109 	/* First, disable everything */
110 	writel(0x0, port[CONSOLE_PORT] + UART_PL011_CR);
111 
112 	/*
113 	 * Set baud rate
114 	 *
115 	 * IBRD = UART_CLK / (16 * BAUD_RATE)
116 	 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
117 	 */
118 	temp = 16 * baudrate;
119 	divider = CONFIG_PL011_CLOCK / temp;
120 	remainder = CONFIG_PL011_CLOCK % temp;
121 	temp = (8 * remainder) / baudrate;
122 	fraction = (temp >> 1) + (temp & 1);
123 
124 	writel(divider, port[CONSOLE_PORT] + UART_PL011_IBRD);
125 	writel(fraction, port[CONSOLE_PORT] + UART_PL011_FBRD);
126 
127 	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
128 	writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN),
129 		port[CONSOLE_PORT] + UART_PL011_LCRH);
130 
131 	/* Finally, enable the UART */
132 	writel((UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE),
133 		port[CONSOLE_PORT] + UART_PL011_CR);
134 
135 	return 0;
136 }
137 
138 #endif /* CONFIG_PL011_SERIAL */
139 
140 void serial_putc (const char c)
141 {
142 	if (c == '\n')
143 		pl01x_putc (CONSOLE_PORT, '\r');
144 
145 	pl01x_putc (CONSOLE_PORT, c);
146 }
147 
148 void serial_puts (const char *s)
149 {
150 	while (*s) {
151 		serial_putc (*s++);
152 	}
153 }
154 
155 int serial_getc (void)
156 {
157 	return pl01x_getc (CONSOLE_PORT);
158 }
159 
160 int serial_tstc (void)
161 {
162 	return pl01x_tstc (CONSOLE_PORT);
163 }
164 
165 void serial_setbrg (void)
166 {
167 	baudrate = gd->baudrate;
168 	serial_init();
169 }
170 
171 static void pl01x_putc (int portnum, char c)
172 {
173 	/* Wait until there is space in the FIFO */
174 	while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
175 		WATCHDOG_RESET();
176 
177 	/* Send the character */
178 	writel(c, port[portnum] + UART_PL01x_DR);
179 }
180 
181 static int pl01x_getc (int portnum)
182 {
183 	unsigned int data;
184 
185 	/* Wait until there is data in the FIFO */
186 	while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
187 		WATCHDOG_RESET();
188 
189 	data = readl(port[portnum] + UART_PL01x_DR);
190 
191 	/* Check for an error flag */
192 	if (data & 0xFFFFFF00) {
193 		/* Clear the error */
194 		writel(0xFFFFFFFF, port[portnum] + UART_PL01x_ECR);
195 		return -1;
196 	}
197 
198 	return (int) data;
199 }
200 
201 static int pl01x_tstc (int portnum)
202 {
203 	WATCHDOG_RESET();
204 	return !(readl(port[portnum] + UART_PL01x_FR) &
205 		 UART_PL01x_FR_RXFE);
206 }
207