1 /* 2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <watchdog.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/clock.h> 13 #include <dm/platform_data/serial_mxc.h> 14 #include <serial.h> 15 #include <linux/compiler.h> 16 17 /* UART Control Register Bit Fields.*/ 18 #define URXD_CHARRDY (1<<15) 19 #define URXD_ERR (1<<14) 20 #define URXD_OVRRUN (1<<13) 21 #define URXD_FRMERR (1<<12) 22 #define URXD_BRK (1<<11) 23 #define URXD_PRERR (1<<10) 24 #define URXD_RX_DATA (0xFF) 25 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 26 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 27 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 28 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 29 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 30 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 31 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 32 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 33 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 34 #define UCR1_SNDBRK (1<<4) /* Send break */ 35 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 36 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 37 #define UCR1_DOZE (1<<1) /* Doze */ 38 #define UCR1_UARTEN (1<<0) /* UART enabled */ 39 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 40 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 41 #define UCR2_CTSC (1<<13) /* CTS pin control */ 42 #define UCR2_CTS (1<<12) /* Clear to send */ 43 #define UCR2_ESCEN (1<<11) /* Escape enable */ 44 #define UCR2_PREN (1<<8) /* Parity enable */ 45 #define UCR2_PROE (1<<7) /* Parity odd/even */ 46 #define UCR2_STPB (1<<6) /* Stop */ 47 #define UCR2_WS (1<<5) /* Word size */ 48 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 49 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 50 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 51 #define UCR2_SRST (1<<0) /* SW reset */ 52 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 53 #define UCR3_PARERREN (1<<12) /* Parity enable */ 54 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 55 #define UCR3_DSR (1<<10) /* Data set ready */ 56 #define UCR3_DCD (1<<9) /* Data carrier detect */ 57 #define UCR3_RI (1<<8) /* Ring indicator */ 58 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 59 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 60 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 61 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 62 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ 63 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ 64 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 65 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 66 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ 67 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 68 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 69 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 70 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 71 #define UCR4_IRSC (1<<5) /* IR special case */ 72 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 73 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 74 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 75 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 76 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 77 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 78 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 79 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 80 #define USR1_RTSS (1<<14) /* RTS pin status */ 81 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 82 #define USR1_RTSD (1<<12) /* RTS delta */ 83 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 84 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 85 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 86 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 87 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 88 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 89 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 90 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 91 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 92 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 93 #define USR2_IDLE (1<<12) /* Idle condition */ 94 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 95 #define USR2_WAKE (1<<7) /* Wake */ 96 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 97 #define USR2_TXDC (1<<3) /* Transmitter complete */ 98 #define USR2_BRCD (1<<2) /* Break condition */ 99 #define USR2_ORE (1<<1) /* Overrun error */ 100 #define USR2_RDR (1<<0) /* Recv data ready */ 101 #define UTS_FRCPERR (1<<13) /* Force parity error */ 102 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 103 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 104 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 105 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 106 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 107 #define UTS_SOFTRST (1<<0) /* Software reset */ 108 109 #ifndef CONFIG_DM_SERIAL 110 111 #ifndef CONFIG_MXC_UART_BASE 112 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" 113 #endif 114 115 #define UART_PHYS CONFIG_MXC_UART_BASE 116 117 #define __REG(x) (*((volatile u32 *)(x))) 118 119 /* Register definitions */ 120 #define URXD 0x0 /* Receiver Register */ 121 #define UTXD 0x40 /* Transmitter Register */ 122 #define UCR1 0x80 /* Control Register 1 */ 123 #define UCR2 0x84 /* Control Register 2 */ 124 #define UCR3 0x88 /* Control Register 3 */ 125 #define UCR4 0x8c /* Control Register 4 */ 126 #define UFCR 0x90 /* FIFO Control Register */ 127 #define USR1 0x94 /* Status Register 1 */ 128 #define USR2 0x98 /* Status Register 2 */ 129 #define UESC 0x9c /* Escape Character Register */ 130 #define UTIM 0xa0 /* Escape Timer Register */ 131 #define UBIR 0xa4 /* BRM Incremental Register */ 132 #define UBMR 0xa8 /* BRM Modulator Register */ 133 #define UBRC 0xac /* Baud Rate Count Register */ 134 #define UTS 0xb4 /* UART Test Register (mx31) */ 135 136 DECLARE_GLOBAL_DATA_PTR; 137 138 static void mxc_serial_setbrg(void) 139 { 140 u32 clk = imx_get_uartclk(); 141 142 if (!gd->baudrate) 143 gd->baudrate = CONFIG_BAUDRATE; 144 145 __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ 146 __REG(UART_PHYS + UBIR) = 0xf; 147 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); 148 149 } 150 151 static int mxc_serial_getc(void) 152 { 153 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) 154 WATCHDOG_RESET(); 155 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ 156 } 157 158 static void mxc_serial_putc(const char c) 159 { 160 __REG(UART_PHYS + UTXD) = c; 161 162 /* wait for transmitter to be ready */ 163 while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) 164 WATCHDOG_RESET(); 165 166 /* If \n, also do \r */ 167 if (c == '\n') 168 serial_putc ('\r'); 169 } 170 171 /* 172 * Test whether a character is in the RX buffer 173 */ 174 static int mxc_serial_tstc(void) 175 { 176 /* If receive fifo is empty, return false */ 177 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) 178 return 0; 179 return 1; 180 } 181 182 /* 183 * Initialise the serial port with the given baudrate. The settings 184 * are always 8 data bits, no parity, 1 stop bit, no start bits. 185 * 186 */ 187 static int mxc_serial_init(void) 188 { 189 __REG(UART_PHYS + UCR1) = 0x0; 190 __REG(UART_PHYS + UCR2) = 0x0; 191 192 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); 193 194 __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP; 195 __REG(UART_PHYS + UCR4) = 0x8000; 196 __REG(UART_PHYS + UESC) = 0x002b; 197 __REG(UART_PHYS + UTIM) = 0x0; 198 199 __REG(UART_PHYS + UTS) = 0x0; 200 201 serial_setbrg(); 202 203 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; 204 205 __REG(UART_PHYS + UCR1) = UCR1_UARTEN; 206 207 return 0; 208 } 209 210 static struct serial_device mxc_serial_drv = { 211 .name = "mxc_serial", 212 .start = mxc_serial_init, 213 .stop = NULL, 214 .setbrg = mxc_serial_setbrg, 215 .putc = mxc_serial_putc, 216 .puts = default_serial_puts, 217 .getc = mxc_serial_getc, 218 .tstc = mxc_serial_tstc, 219 }; 220 221 void mxc_serial_initialize(void) 222 { 223 serial_register(&mxc_serial_drv); 224 } 225 226 __weak struct serial_device *default_serial_console(void) 227 { 228 return &mxc_serial_drv; 229 } 230 #endif 231 232 #ifdef CONFIG_DM_SERIAL 233 234 struct mxc_uart { 235 u32 rxd; 236 u32 spare0[15]; 237 238 u32 txd; 239 u32 spare1[15]; 240 241 u32 cr1; 242 u32 cr2; 243 u32 cr3; 244 u32 cr4; 245 246 u32 fcr; 247 u32 sr1; 248 u32 sr2; 249 u32 esc; 250 251 u32 tim; 252 u32 bir; 253 u32 bmr; 254 u32 brc; 255 256 u32 onems; 257 u32 ts; 258 }; 259 260 int mxc_serial_setbrg(struct udevice *dev, int baudrate) 261 { 262 struct mxc_serial_platdata *plat = dev->platdata; 263 struct mxc_uart *const uart = plat->reg; 264 u32 clk = imx_get_uartclk(); 265 266 writel(4 << 7, &uart->fcr); /* divide input clock by 2 */ 267 writel(0xf, &uart->bir); 268 writel(clk / (2 * baudrate), &uart->bmr); 269 270 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST, 271 &uart->cr2); 272 writel(UCR1_UARTEN, &uart->cr1); 273 274 return 0; 275 } 276 277 static int mxc_serial_probe(struct udevice *dev) 278 { 279 struct mxc_serial_platdata *plat = dev->platdata; 280 struct mxc_uart *const uart = plat->reg; 281 282 writel(0, &uart->cr1); 283 writel(0, &uart->cr2); 284 while (!(readl(&uart->cr2) & UCR2_SRST)); 285 writel(0x704 | UCR3_ADNIMP, &uart->cr3); 286 writel(0x8000, &uart->cr4); 287 writel(0x2b, &uart->esc); 288 writel(0, &uart->tim); 289 writel(0, &uart->ts); 290 291 return 0; 292 } 293 294 static int mxc_serial_getc(struct udevice *dev) 295 { 296 struct mxc_serial_platdata *plat = dev->platdata; 297 struct mxc_uart *const uart = plat->reg; 298 299 if (readl(&uart->ts) & UTS_RXEMPTY) 300 return -EAGAIN; 301 302 return readl(&uart->rxd) & URXD_RX_DATA; 303 } 304 305 static int mxc_serial_putc(struct udevice *dev, const char ch) 306 { 307 struct mxc_serial_platdata *plat = dev->platdata; 308 struct mxc_uart *const uart = plat->reg; 309 310 if (!(readl(&uart->ts) & UTS_TXEMPTY)) 311 return -EAGAIN; 312 313 writel(ch, &uart->txd); 314 315 return 0; 316 } 317 318 static int mxc_serial_pending(struct udevice *dev, bool input) 319 { 320 struct mxc_serial_platdata *plat = dev->platdata; 321 struct mxc_uart *const uart = plat->reg; 322 uint32_t sr2 = readl(&uart->sr2); 323 324 if (input) 325 return sr2 & USR2_RDR ? 1 : 0; 326 else 327 return sr2 & USR2_TXDC ? 0 : 1; 328 } 329 330 static const struct dm_serial_ops mxc_serial_ops = { 331 .putc = mxc_serial_putc, 332 .pending = mxc_serial_pending, 333 .getc = mxc_serial_getc, 334 .setbrg = mxc_serial_setbrg, 335 }; 336 337 U_BOOT_DRIVER(serial_mxc) = { 338 .name = "serial_mxc", 339 .id = UCLASS_SERIAL, 340 .probe = mxc_serial_probe, 341 .ops = &mxc_serial_ops, 342 .flags = DM_FLAG_PRE_RELOC, 343 }; 344 #endif 345