xref: /openbmc/u-boot/drivers/serial/serial_mxc.c (revision 8f3ff11c)
1 /*
2  * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
17  *
18  */
19 
20 #include <common.h>
21 #include <watchdog.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/clock.h>
24 #include <serial.h>
25 #include <linux/compiler.h>
26 
27 #define __REG(x)     (*((volatile u32 *)(x)))
28 
29 #ifndef CONFIG_MXC_UART_BASE
30 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
31 #endif
32 
33 #define UART_PHYS	CONFIG_MXC_UART_BASE
34 
35 /* Register definitions */
36 #define URXD  0x0  /* Receiver Register */
37 #define UTXD  0x40 /* Transmitter Register */
38 #define UCR1  0x80 /* Control Register 1 */
39 #define UCR2  0x84 /* Control Register 2 */
40 #define UCR3  0x88 /* Control Register 3 */
41 #define UCR4  0x8c /* Control Register 4 */
42 #define UFCR  0x90 /* FIFO Control Register */
43 #define USR1  0x94 /* Status Register 1 */
44 #define USR2  0x98 /* Status Register 2 */
45 #define UESC  0x9c /* Escape Character Register */
46 #define UTIM  0xa0 /* Escape Timer Register */
47 #define UBIR  0xa4 /* BRM Incremental Register */
48 #define UBMR  0xa8 /* BRM Modulator Register */
49 #define UBRC  0xac /* Baud Rate Count Register */
50 #define UTS   0xb4 /* UART Test Register (mx31) */
51 
52 /* UART Control Register Bit Fields.*/
53 #define  URXD_CHARRDY    (1<<15)
54 #define  URXD_ERR        (1<<14)
55 #define  URXD_OVRRUN     (1<<13)
56 #define  URXD_FRMERR     (1<<12)
57 #define  URXD_BRK        (1<<11)
58 #define  URXD_PRERR      (1<<10)
59 #define  URXD_RX_DATA    (0xFF)
60 #define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
61 #define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
62 #define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
63 #define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
64 #define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
65 #define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
66 #define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
67 #define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
68 #define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
69 #define  UCR1_SNDBRK     (1<<4)	 /* Send break */
70 #define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
71 #define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
72 #define  UCR1_DOZE       (1<<1)	 /* Doze */
73 #define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
74 #define  UCR2_ESCI	 (1<<15) /* Escape seq interrupt enable */
75 #define  UCR2_IRTS	 (1<<14) /* Ignore RTS pin */
76 #define  UCR2_CTSC	 (1<<13) /* CTS pin control */
77 #define  UCR2_CTS        (1<<12) /* Clear to send */
78 #define  UCR2_ESCEN      (1<<11) /* Escape enable */
79 #define  UCR2_PREN       (1<<8)  /* Parity enable */
80 #define  UCR2_PROE       (1<<7)  /* Parity odd/even */
81 #define  UCR2_STPB       (1<<6)	 /* Stop */
82 #define  UCR2_WS         (1<<5)	 /* Word size */
83 #define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
84 #define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
85 #define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
86 #define  UCR2_SRST	 (1<<0)	 /* SW reset */
87 #define  UCR3_DTREN	 (1<<13) /* DTR interrupt enable */
88 #define  UCR3_PARERREN   (1<<12) /* Parity enable */
89 #define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
90 #define  UCR3_DSR        (1<<10) /* Data set ready */
91 #define  UCR3_DCD        (1<<9)  /* Data carrier detect */
92 #define  UCR3_RI         (1<<8)  /* Ring indicator */
93 #define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
94 #define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
95 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
96 #define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
97 #define  UCR3_REF25	 (1<<3)  /* Ref freq 25 MHz */
98 #define  UCR3_REF30	 (1<<2)  /* Ref Freq 30 MHz */
99 #define  UCR3_INVT	 (1<<1)  /* Inverted Infrared transmission */
100 #define  UCR3_BPEN	 (1<<0)  /* Preset registers enable */
101 #define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
102 #define  UCR4_INVR	 (1<<9)  /* Inverted infrared reception */
103 #define  UCR4_ENIRI	 (1<<8)  /* Serial infrared interrupt enable */
104 #define  UCR4_WKEN	 (1<<7)  /* Wake interrupt enable */
105 #define  UCR4_REF16	 (1<<6)  /* Ref freq 16 MHz */
106 #define  UCR4_IRSC	 (1<<5)  /* IR special case */
107 #define  UCR4_TCEN	 (1<<3)  /* Transmit complete interrupt enable */
108 #define  UCR4_BKEN	 (1<<2)  /* Break condition interrupt enable */
109 #define  UCR4_OREN	 (1<<1)  /* Receiver overrun interrupt enable */
110 #define  UCR4_DREN	 (1<<0)  /* Recv data ready interrupt enable */
111 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
112 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
113 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
114 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
115 #define  USR1_RTSS	 (1<<14) /* RTS pin status */
116 #define  USR1_TRDY	 (1<<13) /* Transmitter ready interrupt/dma flag */
117 #define  USR1_RTSD	 (1<<12) /* RTS delta */
118 #define  USR1_ESCF	 (1<<11) /* Escape seq interrupt flag */
119 #define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
120 #define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
121 #define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
122 #define  USR1_RXDS	 (1<<6)	 /* Receiver idle interrupt flag */
123 #define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
124 #define  USR1_AWAKE	 (1<<4)	 /* Aysnc wake interrupt flag */
125 #define  USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
126 #define  USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
127 #define  USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
128 #define  USR2_IDLE	 (1<<12) /* Idle condition */
129 #define  USR2_IRINT	 (1<<8)	 /* Serial infrared interrupt flag */
130 #define  USR2_WAKE	 (1<<7)	 /* Wake */
131 #define  USR2_RTSF	 (1<<4)	 /* RTS edge interrupt flag */
132 #define  USR2_TXDC	 (1<<3)	 /* Transmitter complete */
133 #define  USR2_BRCD	 (1<<2)	 /* Break condition */
134 #define  USR2_ORE        (1<<1)	 /* Overrun error */
135 #define  USR2_RDR        (1<<0)	 /* Recv data ready */
136 #define  UTS_FRCPERR	 (1<<13) /* Force parity error */
137 #define  UTS_LOOP        (1<<12) /* Loop tx and rx */
138 #define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
139 #define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
140 #define  UTS_TXFULL	 (1<<4)	 /* TxFIFO full */
141 #define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
142 #define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
143 
144 DECLARE_GLOBAL_DATA_PTR;
145 
146 static void mxc_serial_setbrg(void)
147 {
148 	u32 clk = imx_get_uartclk();
149 
150 	if (!gd->baudrate)
151 		gd->baudrate = CONFIG_BAUDRATE;
152 
153 	__REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
154 	__REG(UART_PHYS + UBIR) = 0xf;
155 	__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
156 
157 }
158 
159 static int mxc_serial_getc(void)
160 {
161 	while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
162 		WATCHDOG_RESET();
163 	return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
164 }
165 
166 static void mxc_serial_putc(const char c)
167 {
168 	__REG(UART_PHYS + UTXD) = c;
169 
170 	/* wait for transmitter to be ready */
171 	while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
172 		WATCHDOG_RESET();
173 
174 	/* If \n, also do \r */
175 	if (c == '\n')
176 		serial_putc ('\r');
177 }
178 
179 /*
180  * Test whether a character is in the RX buffer
181  */
182 static int mxc_serial_tstc(void)
183 {
184 	/* If receive fifo is empty, return false */
185 	if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
186 		return 0;
187 	return 1;
188 }
189 
190 /*
191  * Initialise the serial port with the given baudrate. The settings
192  * are always 8 data bits, no parity, 1 stop bit, no start bits.
193  *
194  */
195 static int mxc_serial_init(void)
196 {
197 	__REG(UART_PHYS + UCR1) = 0x0;
198 	__REG(UART_PHYS + UCR2) = 0x0;
199 
200 	while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
201 
202 	__REG(UART_PHYS + UCR3) = 0x0704;
203 	__REG(UART_PHYS + UCR4) = 0x8000;
204 	__REG(UART_PHYS + UESC) = 0x002b;
205 	__REG(UART_PHYS + UTIM) = 0x0;
206 
207 	__REG(UART_PHYS + UTS) = 0x0;
208 
209 	serial_setbrg();
210 
211 	__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
212 
213 	__REG(UART_PHYS + UCR1) = UCR1_UARTEN;
214 
215 	return 0;
216 }
217 
218 static struct serial_device mxc_serial_drv = {
219 	.name	= "mxc_serial",
220 	.start	= mxc_serial_init,
221 	.stop	= NULL,
222 	.setbrg	= mxc_serial_setbrg,
223 	.putc	= mxc_serial_putc,
224 	.puts	= default_serial_puts,
225 	.getc	= mxc_serial_getc,
226 	.tstc	= mxc_serial_tstc,
227 };
228 
229 void mxc_serial_initialize(void)
230 {
231 	serial_register(&mxc_serial_drv);
232 }
233 
234 __weak struct serial_device *default_serial_console(void)
235 {
236 	return &mxc_serial_drv;
237 }
238