1 /* 2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 */ 19 20 #include <common.h> 21 #include <watchdog.h> 22 #ifdef CONFIG_MX31 23 #include <asm/arch/mx31.h> 24 #else 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/clock.h> 27 #endif 28 29 #define __REG(x) (*((volatile u32 *)(x))) 30 31 #if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1) 32 #define UART_PHYS 0x43f90000 33 #elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2) 34 #define UART_PHYS 0x43f94000 35 #elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3) 36 #define UART_PHYS 0x5000c000 37 #elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4) 38 #define UART_PHYS 0x43fb0000 39 #elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5) 40 #define UART_PHYS 0x43fb4000 41 #elif defined(CONFIG_SYS_MX27_UART1) 42 #define UART_PHYS 0x1000a000 43 #elif defined(CONFIG_SYS_MX27_UART2) 44 #define UART_PHYS 0x1000b000 45 #elif defined(CONFIG_SYS_MX27_UART3) 46 #define UART_PHYS 0x1000c000 47 #elif defined(CONFIG_SYS_MX27_UART4) 48 #define UART_PHYS 0x1000d000 49 #elif defined(CONFIG_SYS_MX27_UART5) 50 #define UART_PHYS 0x1001b000 51 #elif defined(CONFIG_SYS_MX27_UART6) 52 #define UART_PHYS 0x1001c000 53 #elif defined(CONFIG_SYS_MX51_UART1) 54 #define UART_PHYS UART1_BASE_ADDR 55 #elif defined(CONFIG_SYS_MX51_UART2) 56 #define UART_PHYS UART2_BASE_ADDR 57 #elif defined(CONFIG_SYS_MX51_UART3) 58 #define UART_PHYS UART3_BASE_ADDR 59 #else 60 #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" 61 #endif 62 63 #ifdef CONFIG_SERIAL_MULTI 64 #warning "MXC driver does not support MULTI serials." 65 #endif 66 67 /* Register definitions */ 68 #define URXD 0x0 /* Receiver Register */ 69 #define UTXD 0x40 /* Transmitter Register */ 70 #define UCR1 0x80 /* Control Register 1 */ 71 #define UCR2 0x84 /* Control Register 2 */ 72 #define UCR3 0x88 /* Control Register 3 */ 73 #define UCR4 0x8c /* Control Register 4 */ 74 #define UFCR 0x90 /* FIFO Control Register */ 75 #define USR1 0x94 /* Status Register 1 */ 76 #define USR2 0x98 /* Status Register 2 */ 77 #define UESC 0x9c /* Escape Character Register */ 78 #define UTIM 0xa0 /* Escape Timer Register */ 79 #define UBIR 0xa4 /* BRM Incremental Register */ 80 #define UBMR 0xa8 /* BRM Modulator Register */ 81 #define UBRC 0xac /* Baud Rate Count Register */ 82 #define UTS 0xb4 /* UART Test Register (mx31) */ 83 84 /* UART Control Register Bit Fields.*/ 85 #define URXD_CHARRDY (1<<15) 86 #define URXD_ERR (1<<14) 87 #define URXD_OVRRUN (1<<13) 88 #define URXD_FRMERR (1<<12) 89 #define URXD_BRK (1<<11) 90 #define URXD_PRERR (1<<10) 91 #define URXD_RX_DATA (0xFF) 92 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 93 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 94 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 95 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 96 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 97 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 98 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 99 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 100 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 101 #define UCR1_SNDBRK (1<<4) /* Send break */ 102 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 103 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 104 #define UCR1_DOZE (1<<1) /* Doze */ 105 #define UCR1_UARTEN (1<<0) /* UART enabled */ 106 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 107 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 108 #define UCR2_CTSC (1<<13) /* CTS pin control */ 109 #define UCR2_CTS (1<<12) /* Clear to send */ 110 #define UCR2_ESCEN (1<<11) /* Escape enable */ 111 #define UCR2_PREN (1<<8) /* Parity enable */ 112 #define UCR2_PROE (1<<7) /* Parity odd/even */ 113 #define UCR2_STPB (1<<6) /* Stop */ 114 #define UCR2_WS (1<<5) /* Word size */ 115 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 116 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 117 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 118 #define UCR2_SRST (1<<0) /* SW reset */ 119 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 120 #define UCR3_PARERREN (1<<12) /* Parity enable */ 121 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 122 #define UCR3_DSR (1<<10) /* Data set ready */ 123 #define UCR3_DCD (1<<9) /* Data carrier detect */ 124 #define UCR3_RI (1<<8) /* Ring indicator */ 125 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 126 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 127 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 128 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 129 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ 130 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ 131 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 132 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 133 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ 134 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 135 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 136 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 137 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 138 #define UCR4_IRSC (1<<5) /* IR special case */ 139 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 140 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 141 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 142 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 143 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 144 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 145 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 146 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 147 #define USR1_RTSS (1<<14) /* RTS pin status */ 148 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 149 #define USR1_RTSD (1<<12) /* RTS delta */ 150 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 151 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 152 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 153 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 154 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 155 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 156 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 157 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 158 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 159 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 160 #define USR2_IDLE (1<<12) /* Idle condition */ 161 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 162 #define USR2_WAKE (1<<7) /* Wake */ 163 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 164 #define USR2_TXDC (1<<3) /* Transmitter complete */ 165 #define USR2_BRCD (1<<2) /* Break condition */ 166 #define USR2_ORE (1<<1) /* Overrun error */ 167 #define USR2_RDR (1<<0) /* Recv data ready */ 168 #define UTS_FRCPERR (1<<13) /* Force parity error */ 169 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 170 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 171 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 172 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 173 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 174 #define UTS_SOFTRST (1<<0) /* Software reset */ 175 176 DECLARE_GLOBAL_DATA_PTR; 177 178 void serial_setbrg (void) 179 { 180 u32 clk = imx_get_uartclk(); 181 182 if (!gd->baudrate) 183 gd->baudrate = CONFIG_BAUDRATE; 184 185 __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ 186 __REG(UART_PHYS + UBIR) = 0xf; 187 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); 188 189 } 190 191 int serial_getc (void) 192 { 193 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) 194 WATCHDOG_RESET(); 195 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ 196 } 197 198 void serial_putc (const char c) 199 { 200 __REG(UART_PHYS + UTXD) = c; 201 202 /* wait for transmitter to be ready */ 203 while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) 204 WATCHDOG_RESET(); 205 206 /* If \n, also do \r */ 207 if (c == '\n') 208 serial_putc ('\r'); 209 } 210 211 /* 212 * Test whether a character is in the RX buffer 213 */ 214 int serial_tstc (void) 215 { 216 /* If receive fifo is empty, return false */ 217 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) 218 return 0; 219 return 1; 220 } 221 222 void 223 serial_puts (const char *s) 224 { 225 while (*s) { 226 serial_putc (*s++); 227 } 228 } 229 230 /* 231 * Initialise the serial port with the given baudrate. The settings 232 * are always 8 data bits, no parity, 1 stop bit, no start bits. 233 * 234 */ 235 int serial_init (void) 236 { 237 __REG(UART_PHYS + UCR1) = 0x0; 238 __REG(UART_PHYS + UCR2) = 0x0; 239 240 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); 241 242 __REG(UART_PHYS + UCR3) = 0x0704; 243 __REG(UART_PHYS + UCR4) = 0x8000; 244 __REG(UART_PHYS + UESC) = 0x002b; 245 __REG(UART_PHYS + UTIM) = 0x0; 246 247 __REG(UART_PHYS + UTS) = 0x0; 248 249 serial_setbrg(); 250 251 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; 252 253 __REG(UART_PHYS + UCR1) = UCR1_UARTEN; 254 255 return 0; 256 } 257