1 /* 2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 */ 19 20 #include <common.h> 21 #ifdef CONFIG_MX31 22 #include <asm/arch/mx31.h> 23 #else 24 #include <asm/arch/imx-regs.h> 25 #include <asm/arch/clock.h> 26 #endif 27 28 #define __REG(x) (*((volatile u32 *)(x))) 29 30 #if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1) 31 #define UART_PHYS 0x43f90000 32 #elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2) 33 #define UART_PHYS 0x43f94000 34 #elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3) 35 #define UART_PHYS 0x5000c000 36 #elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4) 37 #define UART_PHYS 0x43fb0000 38 #elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5) 39 #define UART_PHYS 0x43fb4000 40 #elif defined(CONFIG_SYS_MX27_UART1) 41 #define UART_PHYS 0x1000a000 42 #elif defined(CONFIG_SYS_MX27_UART2) 43 #define UART_PHYS 0x1000b000 44 #elif defined(CONFIG_SYS_MX27_UART3) 45 #define UART_PHYS 0x1000c000 46 #elif defined(CONFIG_SYS_MX27_UART4) 47 #define UART_PHYS 0x1000d000 48 #elif defined(CONFIG_SYS_MX27_UART5) 49 #define UART_PHYS 0x1001b000 50 #elif defined(CONFIG_SYS_MX27_UART6) 51 #define UART_PHYS 0x1001c000 52 #elif defined(CONFIG_SYS_MX51_UART1) 53 #define UART_PHYS UART1_BASE_ADDR 54 #elif defined(CONFIG_SYS_MX51_UART2) 55 #define UART_PHYS UART2_BASE_ADDR 56 #elif defined(CONFIG_SYS_MX51_UART3) 57 #define UART_PHYS UART3_BASE_ADDR 58 #else 59 #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" 60 #endif 61 62 #ifdef CONFIG_SERIAL_MULTI 63 #warning "MXC driver does not support MULTI serials." 64 #endif 65 66 /* Register definitions */ 67 #define URXD 0x0 /* Receiver Register */ 68 #define UTXD 0x40 /* Transmitter Register */ 69 #define UCR1 0x80 /* Control Register 1 */ 70 #define UCR2 0x84 /* Control Register 2 */ 71 #define UCR3 0x88 /* Control Register 3 */ 72 #define UCR4 0x8c /* Control Register 4 */ 73 #define UFCR 0x90 /* FIFO Control Register */ 74 #define USR1 0x94 /* Status Register 1 */ 75 #define USR2 0x98 /* Status Register 2 */ 76 #define UESC 0x9c /* Escape Character Register */ 77 #define UTIM 0xa0 /* Escape Timer Register */ 78 #define UBIR 0xa4 /* BRM Incremental Register */ 79 #define UBMR 0xa8 /* BRM Modulator Register */ 80 #define UBRC 0xac /* Baud Rate Count Register */ 81 #define UTS 0xb4 /* UART Test Register (mx31) */ 82 83 /* UART Control Register Bit Fields.*/ 84 #define URXD_CHARRDY (1<<15) 85 #define URXD_ERR (1<<14) 86 #define URXD_OVRRUN (1<<13) 87 #define URXD_FRMERR (1<<12) 88 #define URXD_BRK (1<<11) 89 #define URXD_PRERR (1<<10) 90 #define URXD_RX_DATA (0xFF) 91 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 92 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 93 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 94 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 95 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 96 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 97 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 98 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 99 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 100 #define UCR1_SNDBRK (1<<4) /* Send break */ 101 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 102 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 103 #define UCR1_DOZE (1<<1) /* Doze */ 104 #define UCR1_UARTEN (1<<0) /* UART enabled */ 105 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 106 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 107 #define UCR2_CTSC (1<<13) /* CTS pin control */ 108 #define UCR2_CTS (1<<12) /* Clear to send */ 109 #define UCR2_ESCEN (1<<11) /* Escape enable */ 110 #define UCR2_PREN (1<<8) /* Parity enable */ 111 #define UCR2_PROE (1<<7) /* Parity odd/even */ 112 #define UCR2_STPB (1<<6) /* Stop */ 113 #define UCR2_WS (1<<5) /* Word size */ 114 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 115 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 116 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 117 #define UCR2_SRST (1<<0) /* SW reset */ 118 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 119 #define UCR3_PARERREN (1<<12) /* Parity enable */ 120 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 121 #define UCR3_DSR (1<<10) /* Data set ready */ 122 #define UCR3_DCD (1<<9) /* Data carrier detect */ 123 #define UCR3_RI (1<<8) /* Ring indicator */ 124 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 125 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 126 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 127 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 128 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ 129 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ 130 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 131 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 132 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ 133 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 134 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 135 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 136 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 137 #define UCR4_IRSC (1<<5) /* IR special case */ 138 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 139 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 140 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 141 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 142 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 143 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 144 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 145 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 146 #define USR1_RTSS (1<<14) /* RTS pin status */ 147 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 148 #define USR1_RTSD (1<<12) /* RTS delta */ 149 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 150 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 151 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 152 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 153 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 154 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 155 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 156 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 157 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 158 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 159 #define USR2_IDLE (1<<12) /* Idle condition */ 160 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 161 #define USR2_WAKE (1<<7) /* Wake */ 162 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 163 #define USR2_TXDC (1<<3) /* Transmitter complete */ 164 #define USR2_BRCD (1<<2) /* Break condition */ 165 #define USR2_ORE (1<<1) /* Overrun error */ 166 #define USR2_RDR (1<<0) /* Recv data ready */ 167 #define UTS_FRCPERR (1<<13) /* Force parity error */ 168 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 169 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 170 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 171 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 172 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 173 #define UTS_SOFTRST (1<<0) /* Software reset */ 174 175 DECLARE_GLOBAL_DATA_PTR; 176 177 void serial_setbrg (void) 178 { 179 u32 clk = imx_get_uartclk(); 180 181 if (!gd->baudrate) 182 gd->baudrate = CONFIG_BAUDRATE; 183 184 __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ 185 __REG(UART_PHYS + UBIR) = 0xf; 186 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); 187 188 } 189 190 int serial_getc (void) 191 { 192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); 193 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ 194 } 195 196 void serial_putc (const char c) 197 { 198 __REG(UART_PHYS + UTXD) = c; 199 200 /* wait for transmitter to be ready */ 201 while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); 202 203 /* If \n, also do \r */ 204 if (c == '\n') 205 serial_putc ('\r'); 206 } 207 208 /* 209 * Test whether a character is in the RX buffer 210 */ 211 int serial_tstc (void) 212 { 213 /* If receive fifo is empty, return false */ 214 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) 215 return 0; 216 return 1; 217 } 218 219 void 220 serial_puts (const char *s) 221 { 222 while (*s) { 223 serial_putc (*s++); 224 } 225 } 226 227 /* 228 * Initialise the serial port with the given baudrate. The settings 229 * are always 8 data bits, no parity, 1 stop bit, no start bits. 230 * 231 */ 232 int serial_init (void) 233 { 234 __REG(UART_PHYS + UCR1) = 0x0; 235 __REG(UART_PHYS + UCR2) = 0x0; 236 237 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); 238 239 __REG(UART_PHYS + UCR3) = 0x0704; 240 __REG(UART_PHYS + UCR4) = 0x8000; 241 __REG(UART_PHYS + UESC) = 0x002b; 242 __REG(UART_PHYS + UTIM) = 0x0; 243 244 __REG(UART_PHYS + UTS) = 0x0; 245 246 serial_setbrg(); 247 248 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; 249 250 __REG(UART_PHYS + UCR1) = UCR1_UARTEN; 251 252 return 0; 253 } 254