1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <watchdog.h>
9 #include <asm/io.h>
10 #include <serial.h>
11 #include <linux/compiler.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
14 
15 #define US1_TDRE	(1 << 7)
16 #define US1_RDRF	(1 << 5)
17 #define US1_OR		(1 << 3)
18 #define UC2_TE		(1 << 3)
19 #define UC2_RE		(1 << 2)
20 #define CFIFO_TXFLUSH	(1 << 7)
21 #define CFIFO_RXFLUSH	(1 << 6)
22 #define SFIFO_RXOF	(1 << 2)
23 #define SFIFO_RXUF	(1 << 0)
24 
25 #define STAT_LBKDIF	(1 << 31)
26 #define STAT_RXEDGIF	(1 << 30)
27 #define STAT_TDRE	(1 << 23)
28 #define STAT_RDRF	(1 << 21)
29 #define STAT_IDLE	(1 << 20)
30 #define STAT_OR		(1 << 19)
31 #define STAT_NF		(1 << 18)
32 #define STAT_FE		(1 << 17)
33 #define STAT_PF		(1 << 16)
34 #define STAT_MA1F	(1 << 15)
35 #define STAT_MA2F	(1 << 14)
36 #define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
37 			 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
38 
39 #define CTRL_TE		(1 << 19)
40 #define CTRL_RE		(1 << 18)
41 
42 #define FIFO_TXFE		0x80
43 #define FIFO_RXFE		0x40
44 
45 #define WATER_TXWATER_OFF	1
46 #define WATER_RXWATER_OFF	16
47 
48 DECLARE_GLOBAL_DATA_PTR;
49 
50 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
51 
52 #ifndef CONFIG_LPUART_32B_REG
53 static void lpuart_serial_setbrg(void)
54 {
55 	u32 clk = mxc_get_clock(MXC_UART_CLK);
56 	u16 sbr;
57 
58 	if (!gd->baudrate)
59 		gd->baudrate = CONFIG_BAUDRATE;
60 
61 	sbr = (u16)(clk / (16 * gd->baudrate));
62 
63 	/* place adjustment later - n/32 BRFA */
64 	__raw_writeb(sbr >> 8, &base->ubdh);
65 	__raw_writeb(sbr & 0xff, &base->ubdl);
66 }
67 
68 static int lpuart_serial_getc(void)
69 {
70 	while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
71 		WATCHDOG_RESET();
72 
73 	barrier();
74 
75 	return __raw_readb(&base->ud);
76 }
77 
78 static void lpuart_serial_putc(const char c)
79 {
80 	if (c == '\n')
81 		lpuart_serial_putc('\r');
82 
83 	while (!(__raw_readb(&base->us1) & US1_TDRE))
84 		WATCHDOG_RESET();
85 
86 	__raw_writeb(c, &base->ud);
87 }
88 
89 /* Test whether a character is in the RX buffer */
90 static int lpuart_serial_tstc(void)
91 {
92 	if (__raw_readb(&base->urcfifo) == 0)
93 		return 0;
94 
95 	return 1;
96 }
97 
98 /*
99  * Initialise the serial port with the given baudrate. The settings
100  * are always 8 data bits, no parity, 1 stop bit, no start bits.
101  */
102 static int lpuart_serial_init(void)
103 {
104 	u8 ctrl;
105 
106 	ctrl = __raw_readb(&base->uc2);
107 	ctrl &= ~UC2_RE;
108 	ctrl &= ~UC2_TE;
109 	__raw_writeb(ctrl, &base->uc2);
110 
111 	__raw_writeb(0, &base->umodem);
112 	__raw_writeb(0, &base->uc1);
113 
114 	/* Disable FIFO and flush buffer */
115 	__raw_writeb(0x0, &base->upfifo);
116 	__raw_writeb(0x0, &base->utwfifo);
117 	__raw_writeb(0x1, &base->urwfifo);
118 	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
119 
120 	/* provide data bits, parity, stop bit, etc */
121 	lpuart_serial_setbrg();
122 
123 	__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
124 
125 	return 0;
126 }
127 
128 static struct serial_device lpuart_serial_drv = {
129 	.name = "lpuart_serial",
130 	.start = lpuart_serial_init,
131 	.stop = NULL,
132 	.setbrg = lpuart_serial_setbrg,
133 	.putc = lpuart_serial_putc,
134 	.puts = default_serial_puts,
135 	.getc = lpuart_serial_getc,
136 	.tstc = lpuart_serial_tstc,
137 };
138 #else
139 static void lpuart32_serial_setbrg(void)
140 {
141 	u32 clk = CONFIG_SYS_CLK_FREQ;
142 	u32 sbr;
143 
144 	if (!gd->baudrate)
145 		gd->baudrate = CONFIG_BAUDRATE;
146 
147 	sbr = (clk / (16 * gd->baudrate));
148 
149 	/* place adjustment later - n/32 BRFA */
150 	out_be32(&base->baud, sbr);
151 }
152 
153 static int lpuart32_serial_getc(void)
154 {
155 	u32 stat;
156 
157 	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
158 		out_be32(&base->stat, STAT_FLAGS);
159 		WATCHDOG_RESET();
160 	}
161 
162 	return in_be32(&base->data) & 0x3ff;
163 }
164 
165 static void lpuart32_serial_putc(const char c)
166 {
167 	if (c == '\n')
168 		lpuart32_serial_putc('\r');
169 
170 	while (!(in_be32(&base->stat) & STAT_TDRE))
171 		WATCHDOG_RESET();
172 
173 	out_be32(&base->data, c);
174 }
175 
176 /* Test whether a character is in the RX buffer */
177 static int lpuart32_serial_tstc(void)
178 {
179 	if ((in_be32(&base->water) >> 24) == 0)
180 		return 0;
181 
182 	return 1;
183 }
184 
185 /*
186  * Initialise the serial port with the given baudrate. The settings
187  * are always 8 data bits, no parity, 1 stop bit, no start bits.
188  */
189 static int lpuart32_serial_init(void)
190 {
191 	u8 ctrl;
192 
193 	ctrl = in_be32(&base->ctrl);
194 	ctrl &= ~CTRL_RE;
195 	ctrl &= ~CTRL_TE;
196 	out_be32(&base->ctrl, ctrl);
197 
198 	out_be32(&base->modir, 0);
199 	out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
200 
201 	out_be32(&base->match, 0);
202 
203 	/* provide data bits, parity, stop bit, etc */
204 	lpuart32_serial_setbrg();
205 
206 	out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
207 
208 	return 0;
209 }
210 
211 static struct serial_device lpuart32_serial_drv = {
212 	.name = "lpuart32_serial",
213 	.start = lpuart32_serial_init,
214 	.stop = NULL,
215 	.setbrg = lpuart32_serial_setbrg,
216 	.putc = lpuart32_serial_putc,
217 	.puts = default_serial_puts,
218 	.getc = lpuart32_serial_getc,
219 	.tstc = lpuart32_serial_tstc,
220 };
221 #endif
222 
223 void lpuart_serial_initialize(void)
224 {
225 #ifdef CONFIG_LPUART_32B_REG
226 	serial_register(&lpuart32_serial_drv);
227 #else
228 	serial_register(&lpuart_serial_drv);
229 #endif
230 }
231 
232 __weak struct serial_device *default_serial_console(void)
233 {
234 #ifdef CONFIG_LPUART_32B_REG
235 	return &lpuart32_serial_drv;
236 #else
237 	return &lpuart_serial_drv;
238 #endif
239 }
240