1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2013 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <fsl_lpuart.h>
10 #include <watchdog.h>
11 #include <asm/io.h>
12 #include <serial.h>
13 #include <linux/compiler.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 
17 #define US1_TDRE	(1 << 7)
18 #define US1_RDRF	(1 << 5)
19 #define US1_OR		(1 << 3)
20 #define UC2_TE		(1 << 3)
21 #define UC2_RE		(1 << 2)
22 #define CFIFO_TXFLUSH	(1 << 7)
23 #define CFIFO_RXFLUSH	(1 << 6)
24 #define SFIFO_RXOF	(1 << 2)
25 #define SFIFO_RXUF	(1 << 0)
26 
27 #define STAT_LBKDIF	(1 << 31)
28 #define STAT_RXEDGIF	(1 << 30)
29 #define STAT_TDRE	(1 << 23)
30 #define STAT_RDRF	(1 << 21)
31 #define STAT_IDLE	(1 << 20)
32 #define STAT_OR		(1 << 19)
33 #define STAT_NF		(1 << 18)
34 #define STAT_FE		(1 << 17)
35 #define STAT_PF		(1 << 16)
36 #define STAT_MA1F	(1 << 15)
37 #define STAT_MA2F	(1 << 14)
38 #define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
39 			 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
40 
41 #define CTRL_TE		(1 << 19)
42 #define CTRL_RE		(1 << 18)
43 
44 #define FIFO_RXFLUSH		BIT(14)
45 #define FIFO_TXFLUSH		BIT(15)
46 #define FIFO_TXSIZE_MASK	0x70
47 #define FIFO_TXSIZE_OFF	4
48 #define FIFO_RXSIZE_MASK	0x7
49 #define FIFO_RXSIZE_OFF	0
50 #define FIFO_TXFE		0x80
51 #ifdef CONFIG_ARCH_IMX8
52 #define FIFO_RXFE		0x08
53 #else
54 #define FIFO_RXFE		0x40
55 #endif
56 
57 #define WATER_TXWATER_OFF	0
58 #define WATER_RXWATER_OFF	16
59 
60 DECLARE_GLOBAL_DATA_PTR;
61 
62 #define LPUART_FLAG_REGMAP_32BIT_REG	BIT(0)
63 #define LPUART_FLAG_REGMAP_ENDIAN_BIG	BIT(1)
64 
65 enum lpuart_devtype {
66 	DEV_VF610 = 1,
67 	DEV_LS1021A,
68 	DEV_MX7ULP,
69 	DEV_IMX8
70 };
71 
72 struct lpuart_serial_platdata {
73 	void *reg;
74 	enum lpuart_devtype devtype;
75 	ulong flags;
76 };
77 
78 static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
79 {
80 	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
81 		if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
82 			*(u32 *)val = in_be32(addr);
83 		else
84 			*(u32 *)val = in_le32(addr);
85 	}
86 }
87 
88 static void lpuart_write32(u32 flags, u32 *addr, u32 val)
89 {
90 	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
91 		if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
92 			out_be32(addr, val);
93 		else
94 			out_le32(addr, val);
95 	}
96 }
97 
98 
99 #ifndef CONFIG_SYS_CLK_FREQ
100 #define CONFIG_SYS_CLK_FREQ	0
101 #endif
102 
103 u32 __weak get_lpuart_clk(void)
104 {
105 	return CONFIG_SYS_CLK_FREQ;
106 }
107 
108 #if IS_ENABLED(CONFIG_CLK)
109 static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
110 {
111 	struct clk per_clk;
112 	ulong rate;
113 	int ret;
114 
115 	ret = clk_get_by_name(dev, "per", &per_clk);
116 	if (ret) {
117 		dev_err(dev, "Failed to get per clk: %d\n", ret);
118 		return ret;
119 	}
120 
121 	rate = clk_get_rate(&per_clk);
122 	if ((long)rate <= 0) {
123 		dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
124 		return ret;
125 	}
126 	*clk = rate;
127 	return 0;
128 }
129 #else
130 static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
131 { return -ENOSYS; }
132 #endif
133 
134 static bool is_lpuart32(struct udevice *dev)
135 {
136 	struct lpuart_serial_platdata *plat = dev->platdata;
137 
138 	return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
139 }
140 
141 static void _lpuart_serial_setbrg(struct udevice *dev,
142 				  int baudrate)
143 {
144 	struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
145 	struct lpuart_fsl *base = plat->reg;
146 	u32 clk;
147 	u16 sbr;
148 	int ret;
149 
150 	if (IS_ENABLED(CONFIG_CLK)) {
151 		ret = get_lpuart_clk_rate(dev, &clk);
152 		if (ret)
153 			return;
154 	} else {
155 		clk = get_lpuart_clk();
156 	}
157 
158 	sbr = (u16)(clk / (16 * baudrate));
159 
160 	/* place adjustment later - n/32 BRFA */
161 	__raw_writeb(sbr >> 8, &base->ubdh);
162 	__raw_writeb(sbr & 0xff, &base->ubdl);
163 }
164 
165 static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
166 {
167 	struct lpuart_fsl *base = plat->reg;
168 	while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
169 		WATCHDOG_RESET();
170 
171 	barrier();
172 
173 	return __raw_readb(&base->ud);
174 }
175 
176 static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
177 				const char c)
178 {
179 	struct lpuart_fsl *base = plat->reg;
180 
181 	while (!(__raw_readb(&base->us1) & US1_TDRE))
182 		WATCHDOG_RESET();
183 
184 	__raw_writeb(c, &base->ud);
185 }
186 
187 /* Test whether a character is in the RX buffer */
188 static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
189 {
190 	struct lpuart_fsl *base = plat->reg;
191 
192 	if (__raw_readb(&base->urcfifo) == 0)
193 		return 0;
194 
195 	return 1;
196 }
197 
198 /*
199  * Initialise the serial port with the given baudrate. The settings
200  * are always 8 data bits, no parity, 1 stop bit, no start bits.
201  */
202 static int _lpuart_serial_init(struct udevice *dev)
203 {
204 	struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
205 	struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
206 	u8 ctrl;
207 
208 	ctrl = __raw_readb(&base->uc2);
209 	ctrl &= ~UC2_RE;
210 	ctrl &= ~UC2_TE;
211 	__raw_writeb(ctrl, &base->uc2);
212 
213 	__raw_writeb(0, &base->umodem);
214 	__raw_writeb(0, &base->uc1);
215 
216 	/* Disable FIFO and flush buffer */
217 	__raw_writeb(0x0, &base->upfifo);
218 	__raw_writeb(0x0, &base->utwfifo);
219 	__raw_writeb(0x1, &base->urwfifo);
220 	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
221 
222 	/* provide data bits, parity, stop bit, etc */
223 	_lpuart_serial_setbrg(dev, gd->baudrate);
224 
225 	__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
226 
227 	return 0;
228 }
229 
230 static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
231 					 int baudrate)
232 {
233 	struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
234 	struct lpuart_fsl_reg32 *base = plat->reg;
235 	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
236 	u32 clk;
237 	int ret;
238 
239 	if (IS_ENABLED(CONFIG_CLK)) {
240 		ret = get_lpuart_clk_rate(dev, &clk);
241 		if (ret)
242 			return;
243 	} else {
244 		clk = get_lpuart_clk();
245 	}
246 
247 	baud_diff = baudrate;
248 	osr = 0;
249 	sbr = 0;
250 
251 	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
252 		tmp_sbr = (clk / (baudrate * tmp_osr));
253 
254 		if (tmp_sbr == 0)
255 			tmp_sbr = 1;
256 
257 		/*calculate difference in actual buad w/ current values */
258 		tmp_diff = (clk / (tmp_osr * tmp_sbr));
259 		tmp_diff = tmp_diff - baudrate;
260 
261 		/* select best values between sbr and sbr+1 */
262 		if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
263 			tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
264 			tmp_sbr++;
265 		}
266 
267 		if (tmp_diff <= baud_diff) {
268 			baud_diff = tmp_diff;
269 			osr = tmp_osr;
270 			sbr = tmp_sbr;
271 		}
272 	}
273 
274 	/*
275 	 * TODO: handle buadrate outside acceptable rate
276 	 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
277 	 * {
278 	 *   Unacceptable baud rate difference of more than 3%
279 	 *   return kStatus_LPUART_BaudrateNotSupport;
280 	 * }
281 	 */
282 	tmp = in_le32(&base->baud);
283 
284 	if ((osr > 3) && (osr < 8))
285 		tmp |= LPUART_BAUD_BOTHEDGE_MASK;
286 
287 	tmp &= ~LPUART_BAUD_OSR_MASK;
288 	tmp |= LPUART_BAUD_OSR(osr-1);
289 
290 	tmp &= ~LPUART_BAUD_SBR_MASK;
291 	tmp |= LPUART_BAUD_SBR(sbr);
292 
293 	/* explicitly disable 10 bit mode & set 1 stop bit */
294 	tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
295 
296 	out_le32(&base->baud, tmp);
297 }
298 
299 static void _lpuart32_serial_setbrg(struct udevice *dev,
300 				    int baudrate)
301 {
302 	struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
303 	struct lpuart_fsl_reg32 *base = plat->reg;
304 	u32 clk;
305 	u32 sbr;
306 	int ret;
307 
308 	if (IS_ENABLED(CONFIG_CLK)) {
309 		ret = get_lpuart_clk_rate(dev, &clk);
310 		if (ret)
311 			return;
312 	} else {
313 		clk = get_lpuart_clk();
314 	}
315 
316 	sbr = (clk / (16 * baudrate));
317 
318 	/* place adjustment later - n/32 BRFA */
319 	lpuart_write32(plat->flags, &base->baud, sbr);
320 }
321 
322 static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
323 {
324 	struct lpuart_fsl_reg32 *base = plat->reg;
325 	u32 stat, val;
326 
327 	lpuart_read32(plat->flags, &base->stat, &stat);
328 	while ((stat & STAT_RDRF) == 0) {
329 		lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
330 		WATCHDOG_RESET();
331 		lpuart_read32(plat->flags, &base->stat, &stat);
332 	}
333 
334 	lpuart_read32(plat->flags, &base->data, &val);
335 
336 	lpuart_read32(plat->flags, &base->stat, &stat);
337 	if (stat & STAT_OR)
338 		lpuart_write32(plat->flags, &base->stat, STAT_OR);
339 
340 	return val & 0x3ff;
341 }
342 
343 static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
344 				  const char c)
345 {
346 	struct lpuart_fsl_reg32 *base = plat->reg;
347 	u32 stat;
348 
349 	if (c == '\n')
350 		serial_putc('\r');
351 
352 	while (true) {
353 		lpuart_read32(plat->flags, &base->stat, &stat);
354 
355 		if ((stat & STAT_TDRE))
356 			break;
357 
358 		WATCHDOG_RESET();
359 	}
360 
361 	lpuart_write32(plat->flags, &base->data, c);
362 }
363 
364 /* Test whether a character is in the RX buffer */
365 static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
366 {
367 	struct lpuart_fsl_reg32 *base = plat->reg;
368 	u32 water;
369 
370 	lpuart_read32(plat->flags, &base->water, &water);
371 
372 	if ((water >> 24) == 0)
373 		return 0;
374 
375 	return 1;
376 }
377 
378 /*
379  * Initialise the serial port with the given baudrate. The settings
380  * are always 8 data bits, no parity, 1 stop bit, no start bits.
381  */
382 static int _lpuart32_serial_init(struct udevice *dev)
383 {
384 	struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
385 	struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
386 	u32 val, tx_fifo_size;
387 
388 	lpuart_read32(plat->flags, &base->ctrl, &val);
389 	val &= ~CTRL_RE;
390 	val &= ~CTRL_TE;
391 	lpuart_write32(plat->flags, &base->ctrl, val);
392 
393 	lpuart_write32(plat->flags, &base->modir, 0);
394 
395 	lpuart_read32(plat->flags, &base->fifo, &val);
396 	tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
397 	/* Set the TX water to half of FIFO size */
398 	if (tx_fifo_size > 1)
399 		tx_fifo_size = tx_fifo_size >> 1;
400 
401 	/* Set RX water to 0, to be triggered by any receive data */
402 	lpuart_write32(plat->flags, &base->water,
403 		       (tx_fifo_size << WATER_TXWATER_OFF));
404 
405 	/* Enable TX and RX FIFO */
406 	val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
407 	lpuart_write32(plat->flags, &base->fifo, val);
408 
409 	lpuart_write32(plat->flags, &base->match, 0);
410 
411 	if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
412 		_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
413 	} else {
414 		/* provide data bits, parity, stop bit, etc */
415 		_lpuart32_serial_setbrg(dev, gd->baudrate);
416 	}
417 
418 	lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
419 
420 	return 0;
421 }
422 
423 static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
424 {
425 	struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
426 
427 	if (is_lpuart32(dev)) {
428 		if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
429 			_lpuart32_serial_setbrg_7ulp(dev, baudrate);
430 		else
431 			_lpuart32_serial_setbrg(dev, baudrate);
432 	} else {
433 		_lpuart_serial_setbrg(dev, baudrate);
434 	}
435 
436 	return 0;
437 }
438 
439 static int lpuart_serial_getc(struct udevice *dev)
440 {
441 	struct lpuart_serial_platdata *plat = dev->platdata;
442 
443 	if (is_lpuart32(dev))
444 		return _lpuart32_serial_getc(plat);
445 
446 	return _lpuart_serial_getc(plat);
447 }
448 
449 static int lpuart_serial_putc(struct udevice *dev, const char c)
450 {
451 	struct lpuart_serial_platdata *plat = dev->platdata;
452 
453 	if (is_lpuart32(dev))
454 		_lpuart32_serial_putc(plat, c);
455 	else
456 		_lpuart_serial_putc(plat, c);
457 
458 	return 0;
459 }
460 
461 static int lpuart_serial_pending(struct udevice *dev, bool input)
462 {
463 	struct lpuart_serial_platdata *plat = dev->platdata;
464 	struct lpuart_fsl *reg = plat->reg;
465 	struct lpuart_fsl_reg32 *reg32 = plat->reg;
466 	u32 stat;
467 
468 	if (is_lpuart32(dev)) {
469 		if (input) {
470 			return _lpuart32_serial_tstc(plat);
471 		} else {
472 			lpuart_read32(plat->flags, &reg32->stat, &stat);
473 			return stat & STAT_TDRE ? 0 : 1;
474 		}
475 	}
476 
477 	if (input)
478 		return _lpuart_serial_tstc(plat);
479 	else
480 		return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
481 }
482 
483 static int lpuart_serial_probe(struct udevice *dev)
484 {
485 	if (is_lpuart32(dev))
486 		return _lpuart32_serial_init(dev);
487 	else
488 		return _lpuart_serial_init(dev);
489 }
490 
491 static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
492 {
493 	struct lpuart_serial_platdata *plat = dev->platdata;
494 	const void *blob = gd->fdt_blob;
495 	int node = dev_of_offset(dev);
496 	fdt_addr_t addr;
497 
498 	addr = devfdt_get_addr(dev);
499 	if (addr == FDT_ADDR_T_NONE)
500 		return -EINVAL;
501 
502 	plat->reg = (void *)addr;
503 	plat->flags = dev_get_driver_data(dev);
504 
505 	if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
506 		plat->devtype = DEV_LS1021A;
507 	else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
508 		plat->devtype = DEV_MX7ULP;
509 	else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
510 		plat->devtype = DEV_VF610;
511 	else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
512 		plat->devtype = DEV_IMX8;
513 
514 	return 0;
515 }
516 
517 static const struct dm_serial_ops lpuart_serial_ops = {
518 	.putc = lpuart_serial_putc,
519 	.pending = lpuart_serial_pending,
520 	.getc = lpuart_serial_getc,
521 	.setbrg = lpuart_serial_setbrg,
522 };
523 
524 static const struct udevice_id lpuart_serial_ids[] = {
525 	{ .compatible = "fsl,ls1021a-lpuart", .data =
526 		LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
527 	{ .compatible = "fsl,imx7ulp-lpuart",
528 		.data = LPUART_FLAG_REGMAP_32BIT_REG },
529 	{ .compatible = "fsl,vf610-lpuart"},
530 	{ .compatible = "fsl,imx8qm-lpuart",
531 		.data = LPUART_FLAG_REGMAP_32BIT_REG },
532 	{ }
533 };
534 
535 U_BOOT_DRIVER(serial_lpuart) = {
536 	.name	= "serial_lpuart",
537 	.id	= UCLASS_SERIAL,
538 	.of_match = lpuart_serial_ids,
539 	.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
540 	.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
541 	.probe = lpuart_serial_probe,
542 	.ops	= &lpuart_serial_ops,
543 	.flags = DM_FLAG_PRE_RELOC,
544 };
545