1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <watchdog.h>
9 #include <asm/io.h>
10 #include <serial.h>
11 #include <linux/compiler.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
14 
15 #define US1_TDRE        (1 << 7)
16 #define US1_RDRF        (1 << 5)
17 #define US1_OR          (1 << 3)
18 #define UC2_TE          (1 << 3)
19 #define UC2_RE          (1 << 2)
20 #define CFIFO_TXFLUSH   (1 << 7)
21 #define CFIFO_RXFLUSH   (1 << 6)
22 #define SFIFO_RXOF      (1 << 2)
23 #define SFIFO_RXUF      (1 << 0)
24 
25 #define STAT_LBKDIF	(1 << 31)
26 #define STAT_RXEDGIF	(1 << 30)
27 #define STAT_TDRE	(1 << 23)
28 #define STAT_RDRF	(1 << 21)
29 #define STAT_IDLE	(1 << 20)
30 #define STAT_OR		(1 << 19)
31 #define STAT_NF		(1 << 18)
32 #define STAT_FE		(1 << 17)
33 #define STAT_PF		(1 << 16)
34 #define STAT_MA1F	(1 << 15)
35 #define STAT_MA2F	(1 << 14)
36 #define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
37 			STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
38 
39 #define CTRL_TE		(1 << 19)
40 #define CTRL_RE		(1 << 18)
41 
42 #define FIFO_TXFE		0x80
43 #define FIFO_RXFE		0x40
44 
45 #define WATER_TXWATER_OFF	1
46 #define WATER_RXWATER_OFF	16
47 
48 DECLARE_GLOBAL_DATA_PTR;
49 
50 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
51 
52 #ifndef CONFIG_LPUART_32B_REG
53 static void lpuart_serial_setbrg(void)
54 {
55 	u32 clk = mxc_get_clock(MXC_UART_CLK);
56 	u16 sbr;
57 
58 	if (!gd->baudrate)
59 		gd->baudrate = CONFIG_BAUDRATE;
60 
61 	sbr = (u16)(clk / (16 * gd->baudrate));
62 	/* place adjustment later - n/32 BRFA */
63 
64 	__raw_writeb(sbr >> 8, &base->ubdh);
65 	__raw_writeb(sbr & 0xff, &base->ubdl);
66 }
67 
68 static int lpuart_serial_getc(void)
69 {
70 	while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
71 		WATCHDOG_RESET();
72 
73 	barrier();
74 
75 	return __raw_readb(&base->ud);
76 }
77 
78 static void lpuart_serial_putc(const char c)
79 {
80 	if (c == '\n')
81 		serial_putc('\r');
82 
83 	while (!(__raw_readb(&base->us1) & US1_TDRE))
84 		WATCHDOG_RESET();
85 
86 	__raw_writeb(c, &base->ud);
87 }
88 
89 /*
90  * Test whether a character is in the RX buffer
91  */
92 static int lpuart_serial_tstc(void)
93 {
94 	if (__raw_readb(&base->urcfifo) == 0)
95 		return 0;
96 
97 	return 1;
98 }
99 
100 /*
101  * Initialise the serial port with the given baudrate. The settings
102  * are always 8 data bits, no parity, 1 stop bit, no start bits.
103  */
104 static int lpuart_serial_init(void)
105 {
106 	u8 ctrl;
107 
108 	ctrl = __raw_readb(&base->uc2);
109 	ctrl &= ~UC2_RE;
110 	ctrl &= ~UC2_TE;
111 	__raw_writeb(ctrl, &base->uc2);
112 
113 	__raw_writeb(0, &base->umodem);
114 	__raw_writeb(0, &base->uc1);
115 
116 	/* Disable FIFO and flush buffer */
117 	__raw_writeb(0x0, &base->upfifo);
118 	__raw_writeb(0x0, &base->utwfifo);
119 	__raw_writeb(0x1, &base->urwfifo);
120 	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
121 
122 	/* provide data bits, parity, stop bit, etc */
123 
124 	serial_setbrg();
125 
126 	__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
127 
128 	return 0;
129 }
130 
131 static struct serial_device lpuart_serial_drv = {
132 	.name = "lpuart_serial",
133 	.start = lpuart_serial_init,
134 	.stop = NULL,
135 	.setbrg = lpuart_serial_setbrg,
136 	.putc = lpuart_serial_putc,
137 	.puts = default_serial_puts,
138 	.getc = lpuart_serial_getc,
139 	.tstc = lpuart_serial_tstc,
140 };
141 #else
142 static void lpuart32_serial_setbrg(void)
143 {
144 	u32 clk = CONFIG_SYS_CLK_FREQ;
145 	u32 sbr;
146 
147 	if (!gd->baudrate)
148 		gd->baudrate = CONFIG_BAUDRATE;
149 
150 	sbr = (clk / (16 * gd->baudrate));
151 	/* place adjustment later - n/32 BRFA */
152 
153 	out_be32(&base->baud, sbr);
154 }
155 
156 static int lpuart32_serial_getc(void)
157 {
158 	u32 stat;
159 
160 	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
161 		out_be32(&base->stat, STAT_FLAGS);
162 		WATCHDOG_RESET();
163 	}
164 
165 	return in_be32(&base->data) & 0x3ff;
166 }
167 
168 static void lpuart32_serial_putc(const char c)
169 {
170 	if (c == '\n')
171 		serial_putc('\r');
172 
173 	while (!(in_be32(&base->stat) & STAT_TDRE))
174 		WATCHDOG_RESET();
175 
176 	out_be32(&base->data, c);
177 }
178 
179 /*
180  * Test whether a character is in the RX buffer
181  */
182 static int lpuart32_serial_tstc(void)
183 {
184 	if ((in_be32(&base->water) >> 24) == 0)
185 		return 0;
186 
187 	return 1;
188 }
189 
190 /*
191  * Initialise the serial port with the given baudrate. The settings
192  * are always 8 data bits, no parity, 1 stop bit, no start bits.
193  */
194 static int lpuart32_serial_init(void)
195 {
196 	u8 ctrl;
197 
198 	ctrl = in_be32(&base->ctrl);
199 	ctrl &= ~CTRL_RE;
200 	ctrl &= ~CTRL_TE;
201 	out_be32(&base->ctrl, ctrl);
202 
203 	out_be32(&base->modir, 0);
204 	out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
205 
206 	out_be32(&base->match, 0);
207 	/* provide data bits, parity, stop bit, etc */
208 
209 	serial_setbrg();
210 
211 	out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
212 
213 	return 0;
214 }
215 
216 static struct serial_device lpuart32_serial_drv = {
217 	.name = "lpuart32_serial",
218 	.start = lpuart32_serial_init,
219 	.stop = NULL,
220 	.setbrg = lpuart32_serial_setbrg,
221 	.putc = lpuart32_serial_putc,
222 	.puts = default_serial_puts,
223 	.getc = lpuart32_serial_getc,
224 	.tstc = lpuart32_serial_tstc,
225 };
226 #endif
227 
228 void lpuart_serial_initialize(void)
229 {
230 #ifdef CONFIG_LPUART_32B_REG
231 	serial_register(&lpuart32_serial_drv);
232 #else
233 	serial_register(&lpuart_serial_drv);
234 #endif
235 }
236 
237 __weak struct serial_device *default_serial_console(void)
238 {
239 #ifdef CONFIG_LPUART_32B_REG
240 	return &lpuart32_serial_drv;
241 #else
242 	return &lpuart_serial_drv;
243 #endif
244 }
245