1 /* 2 * COM1 NS16550 support 3 * originally from linux source (arch/powerpc/boot/ns16550.c) 4 * modified to use CONFIG_SYS_ISA_MEM and new defines 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <reset.h> 13 #include <serial.h> 14 #include <watchdog.h> 15 #include <linux/types.h> 16 #include <asm/io.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ 21 #define UART_MCRVAL (UART_MCR_DTR | \ 22 UART_MCR_RTS) /* RTS/DTR */ 23 24 #ifndef CONFIG_DM_SERIAL 25 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 26 #define serial_out(x, y) outb(x, (ulong)y) 27 #define serial_in(y) inb((ulong)y) 28 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0) 29 #define serial_out(x, y) out_be32(y, x) 30 #define serial_in(y) in_be32(y) 31 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0) 32 #define serial_out(x, y) out_le32(y, x) 33 #define serial_in(y) in_le32(y) 34 #else 35 #define serial_out(x, y) writeb(x, y) 36 #define serial_in(y) readb(y) 37 #endif 38 #endif /* !CONFIG_DM_SERIAL */ 39 40 #if defined(CONFIG_SOC_KEYSTONE) 41 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 42 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) 43 #undef UART_MCRVAL 44 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL 45 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) 46 #else 47 #define UART_MCRVAL (UART_MCR_RTS) 48 #endif 49 #endif 50 51 #ifndef CONFIG_SYS_NS16550_IER 52 #define CONFIG_SYS_NS16550_IER 0x00 53 #endif /* CONFIG_SYS_NS16550_IER */ 54 55 static inline void serial_out_shift(void *addr, int shift, int value) 56 { 57 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 58 outb(value, (ulong)addr); 59 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) 60 out_le32(addr, value); 61 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 62 out_be32(addr, value); 63 #elif defined(CONFIG_SYS_NS16550_MEM32) 64 writel(value, addr); 65 #elif defined(CONFIG_SYS_BIG_ENDIAN) 66 writeb(value, addr + (1 << shift) - 1); 67 #else 68 writeb(value, addr); 69 #endif 70 } 71 72 static inline int serial_in_shift(void *addr, int shift) 73 { 74 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 75 return inb((ulong)addr); 76 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) 77 return in_le32(addr); 78 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 79 return in_be32(addr); 80 #elif defined(CONFIG_SYS_NS16550_MEM32) 81 return readl(addr); 82 #elif defined(CONFIG_SYS_BIG_ENDIAN) 83 return readb(addr + (1 << shift) - 1); 84 #else 85 return readb(addr); 86 #endif 87 } 88 89 #ifdef CONFIG_DM_SERIAL 90 91 #ifndef CONFIG_SYS_NS16550_CLK 92 #define CONFIG_SYS_NS16550_CLK 0 93 #endif 94 95 static void ns16550_writeb(NS16550_t port, int offset, int value) 96 { 97 struct ns16550_platdata *plat = port->plat; 98 unsigned char *addr; 99 100 offset *= 1 << plat->reg_shift; 101 addr = (unsigned char *)plat->base + offset; 102 103 /* 104 * As far as we know it doesn't make sense to support selection of 105 * these options at run-time, so use the existing CONFIG options. 106 */ 107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); 108 } 109 110 static int ns16550_readb(NS16550_t port, int offset) 111 { 112 struct ns16550_platdata *plat = port->plat; 113 unsigned char *addr; 114 115 offset *= 1 << plat->reg_shift; 116 addr = (unsigned char *)plat->base + offset; 117 118 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); 119 } 120 121 static u32 ns16550_getfcr(NS16550_t port) 122 { 123 struct ns16550_platdata *plat = port->plat; 124 125 return plat->fcr; 126 } 127 128 /* We can clean these up once everything is moved to driver model */ 129 #define serial_out(value, addr) \ 130 ns16550_writeb(com_port, \ 131 (unsigned char *)addr - (unsigned char *)com_port, value) 132 #define serial_in(addr) \ 133 ns16550_readb(com_port, \ 134 (unsigned char *)addr - (unsigned char *)com_port) 135 #else 136 static u32 ns16550_getfcr(NS16550_t port) 137 { 138 return UART_FCR_DEFVAL; 139 } 140 #endif 141 142 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) 143 { 144 const unsigned int mode_x_div = 16; 145 146 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); 147 } 148 149 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) 150 { 151 /* to keep serial format, read lcr before writing BKSE */ 152 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; 153 154 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr); 155 serial_out(baud_divisor & 0xff, &com_port->dll); 156 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); 157 serial_out(lcr_val, &com_port->lcr); 158 } 159 160 void NS16550_init(NS16550_t com_port, int baud_divisor) 161 { 162 #if (defined(CONFIG_SPL_BUILD) && \ 163 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) 164 /* 165 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode 166 * before SPL starts only THRE bit is set. We have to empty the 167 * transmitter before initialization starts. 168 */ 169 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) 170 == UART_LSR_THRE) { 171 if (baud_divisor != -1) 172 NS16550_setbrg(com_port, baud_divisor); 173 serial_out(0, &com_port->mdr1); 174 } 175 #endif 176 177 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) 178 ; 179 180 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 181 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL) 182 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ 183 #endif 184 185 serial_out(UART_MCRVAL, &com_port->mcr); 186 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 187 /* initialize serial config to 8N1 before writing baudrate */ 188 serial_out(UART_LCRVAL, &com_port->lcr); 189 if (baud_divisor != -1) 190 NS16550_setbrg(com_port, baud_divisor); 191 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \ 192 defined(CONFIG_OMAP_SERIAL) 193 /* /16 is proper to hit 115200 with 48MHz */ 194 serial_out(0, &com_port->mdr1); 195 #endif 196 #if defined(CONFIG_SOC_KEYSTONE) 197 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); 198 #endif 199 } 200 201 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 202 void NS16550_reinit(NS16550_t com_port, int baud_divisor) 203 { 204 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 205 NS16550_setbrg(com_port, 0); 206 serial_out(UART_MCRVAL, &com_port->mcr); 207 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 208 NS16550_setbrg(com_port, baud_divisor); 209 } 210 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 211 212 void NS16550_putc(NS16550_t com_port, char c) 213 { 214 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) 215 ; 216 serial_out(c, &com_port->thr); 217 218 /* 219 * Call watchdog_reset() upon newline. This is done here in putc 220 * since the environment code uses a single puts() to print the complete 221 * environment upon "printenv". So we can't put this watchdog call 222 * in puts(). 223 */ 224 if (c == '\n') 225 WATCHDOG_RESET(); 226 } 227 228 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 229 char NS16550_getc(NS16550_t com_port) 230 { 231 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { 232 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY) 233 extern void usbtty_poll(void); 234 usbtty_poll(); 235 #endif 236 WATCHDOG_RESET(); 237 } 238 return serial_in(&com_port->rbr); 239 } 240 241 int NS16550_tstc(NS16550_t com_port) 242 { 243 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; 244 } 245 246 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 247 248 #ifdef CONFIG_DEBUG_UART_NS16550 249 250 #include <debug_uart.h> 251 252 static inline void _debug_uart_init(void) 253 { 254 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 255 int baud_divisor; 256 257 /* 258 * We copy the code from above because it is already horribly messy. 259 * Trying to refactor to nicely remove the duplication doesn't seem 260 * feasible. The better fix is to move all users of this driver to 261 * driver model. 262 */ 263 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, 264 CONFIG_BAUDRATE); 265 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); 266 serial_dout(&com_port->mcr, UART_MCRVAL); 267 serial_dout(&com_port->fcr, UART_FCR_DEFVAL); 268 269 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); 270 serial_dout(&com_port->dll, baud_divisor & 0xff); 271 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); 272 serial_dout(&com_port->lcr, UART_LCRVAL); 273 } 274 275 static inline int NS16550_read_baud_divisor(struct NS16550 *com_port) 276 { 277 int ret; 278 279 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); 280 ret = serial_din(&com_port->dll) & 0xff; 281 ret |= (serial_din(&com_port->dlm) & 0xff) << 8; 282 serial_dout(&com_port->lcr, UART_LCRVAL); 283 284 return ret; 285 } 286 287 static inline void _debug_uart_putc(int ch) 288 { 289 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 290 291 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) { 292 if (!NS16550_read_baud_divisor(com_port)) 293 return; 294 } 295 serial_dout(&com_port->thr, ch); 296 } 297 298 DEBUG_UART_FUNCS 299 300 #endif 301 302 #ifdef CONFIG_DM_SERIAL 303 static int ns16550_serial_putc(struct udevice *dev, const char ch) 304 { 305 struct NS16550 *const com_port = dev_get_priv(dev); 306 307 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) 308 return -EAGAIN; 309 serial_out(ch, &com_port->thr); 310 311 /* 312 * Call watchdog_reset() upon newline. This is done here in putc 313 * since the environment code uses a single puts() to print the complete 314 * environment upon "printenv". So we can't put this watchdog call 315 * in puts(). 316 */ 317 if (ch == '\n') 318 WATCHDOG_RESET(); 319 320 return 0; 321 } 322 323 static int ns16550_serial_pending(struct udevice *dev, bool input) 324 { 325 struct NS16550 *const com_port = dev_get_priv(dev); 326 327 if (input) 328 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0; 329 else 330 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1; 331 } 332 333 static int ns16550_serial_getc(struct udevice *dev) 334 { 335 struct NS16550 *const com_port = dev_get_priv(dev); 336 337 if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) 338 return -EAGAIN; 339 340 return serial_in(&com_port->rbr); 341 } 342 343 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) 344 { 345 struct NS16550 *const com_port = dev_get_priv(dev); 346 struct ns16550_platdata *plat = com_port->plat; 347 int clock_divisor; 348 349 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); 350 351 NS16550_setbrg(com_port, clock_divisor); 352 353 return 0; 354 } 355 356 static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) 357 { 358 struct NS16550 *const com_port = dev_get_priv(dev); 359 int lcr_val = UART_LCR_WLS_8; 360 uint parity = SERIAL_GET_PARITY(serial_config); 361 uint bits = SERIAL_GET_BITS(serial_config); 362 uint stop = SERIAL_GET_STOP(serial_config); 363 364 /* 365 * only parity config is implemented, check if other serial settings 366 * are the default one. 367 */ 368 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP) 369 return -ENOTSUPP; /* not supported in driver*/ 370 371 switch (parity) { 372 case SERIAL_PAR_NONE: 373 /* no bits to add */ 374 break; 375 case SERIAL_PAR_ODD: 376 lcr_val |= UART_LCR_PEN; 377 break; 378 case SERIAL_PAR_EVEN: 379 lcr_val |= UART_LCR_PEN | UART_LCR_EPS; 380 break; 381 default: 382 return -ENOTSUPP; /* not supported in driver*/ 383 } 384 385 serial_out(lcr_val, &com_port->lcr); 386 return 0; 387 } 388 389 int ns16550_serial_probe(struct udevice *dev) 390 { 391 struct NS16550 *const com_port = dev_get_priv(dev); 392 struct reset_ctl_bulk reset_bulk; 393 int ret; 394 395 ret = reset_get_bulk(dev, &reset_bulk); 396 if (!ret) 397 reset_deassert_bulk(&reset_bulk); 398 399 com_port->plat = dev_get_platdata(dev); 400 NS16550_init(com_port, -1); 401 402 return 0; 403 } 404 405 #if CONFIG_IS_ENABLED(OF_CONTROL) 406 enum { 407 PORT_NS16550 = 0, 408 PORT_JZ4780, 409 }; 410 #endif 411 412 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 413 int ns16550_serial_ofdata_to_platdata(struct udevice *dev) 414 { 415 struct ns16550_platdata *plat = dev->platdata; 416 const u32 port_type = dev_get_driver_data(dev); 417 fdt_addr_t addr; 418 struct clk clk; 419 int err; 420 421 /* try Processor Local Bus device first */ 422 addr = dev_read_addr(dev); 423 #if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI) 424 if (addr == FDT_ADDR_T_NONE) { 425 /* then try pci device */ 426 struct fdt_pci_addr pci_addr; 427 u32 bar; 428 int ret; 429 430 /* we prefer to use a memory-mapped register */ 431 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev), 432 FDT_PCI_SPACE_MEM32, "reg", 433 &pci_addr); 434 if (ret) { 435 /* try if there is any i/o-mapped register */ 436 ret = fdtdec_get_pci_addr(gd->fdt_blob, 437 dev_of_offset(dev), 438 FDT_PCI_SPACE_IO, 439 "reg", &pci_addr); 440 if (ret) 441 return ret; 442 } 443 444 ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar); 445 if (ret) 446 return ret; 447 448 addr = bar; 449 } 450 #endif 451 452 if (addr == FDT_ADDR_T_NONE) 453 return -EINVAL; 454 455 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 456 plat->base = addr; 457 #else 458 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); 459 #endif 460 461 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); 462 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); 463 464 err = clk_get_by_index(dev, 0, &clk); 465 if (!err) { 466 err = clk_get_rate(&clk); 467 if (!IS_ERR_VALUE(err)) 468 plat->clock = err; 469 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { 470 debug("ns16550 failed to get clock\n"); 471 return err; 472 } 473 474 if (!plat->clock) 475 plat->clock = dev_read_u32_default(dev, "clock-frequency", 476 CONFIG_SYS_NS16550_CLK); 477 if (!plat->clock) { 478 debug("ns16550 clock not defined\n"); 479 return -EINVAL; 480 } 481 482 plat->fcr = UART_FCR_DEFVAL; 483 if (port_type == PORT_JZ4780) 484 plat->fcr |= UART_FCR_UME; 485 486 return 0; 487 } 488 #endif 489 490 const struct dm_serial_ops ns16550_serial_ops = { 491 .putc = ns16550_serial_putc, 492 .pending = ns16550_serial_pending, 493 .getc = ns16550_serial_getc, 494 .setbrg = ns16550_serial_setbrg, 495 .setconfig = ns16550_serial_setconfig 496 }; 497 498 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 499 /* 500 * Please consider existing compatible strings before adding a new 501 * one to keep this table compact. Or you may add a generic "ns16550" 502 * compatible string to your dts. 503 */ 504 static const struct udevice_id ns16550_serial_ids[] = { 505 { .compatible = "ns16550", .data = PORT_NS16550 }, 506 { .compatible = "ns16550a", .data = PORT_NS16550 }, 507 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, 508 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, 509 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, 510 {} 511 }; 512 #endif /* OF_CONTROL && !OF_PLATDATA */ 513 514 #if CONFIG_IS_ENABLED(SERIAL_PRESENT) 515 516 /* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */ 517 #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL) 518 U_BOOT_DRIVER(ns16550_serial) = { 519 .name = "ns16550_serial", 520 .id = UCLASS_SERIAL, 521 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 522 .of_match = ns16550_serial_ids, 523 .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata, 524 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), 525 #endif 526 .priv_auto_alloc_size = sizeof(struct NS16550), 527 .probe = ns16550_serial_probe, 528 .ops = &ns16550_serial_ops, 529 #if !CONFIG_IS_ENABLED(OF_CONTROL) 530 .flags = DM_FLAG_PRE_RELOC, 531 #endif 532 }; 533 #endif 534 #endif /* SERIAL_PRESENT */ 535 536 #endif /* CONFIG_DM_SERIAL */ 537