1 /* 2 * COM1 NS16550 support 3 * originally from linux source (arch/powerpc/boot/ns16550.c) 4 * modified to use CONFIG_SYS_ISA_MEM and new defines 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <reset.h> 13 #include <serial.h> 14 #include <watchdog.h> 15 #include <linux/types.h> 16 #include <asm/io.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ 21 #define UART_MCRVAL (UART_MCR_DTR | \ 22 UART_MCR_RTS) /* RTS/DTR */ 23 24 #ifndef CONFIG_DM_SERIAL 25 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 26 #define serial_out(x, y) outb(x, (ulong)y) 27 #define serial_in(y) inb((ulong)y) 28 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0) 29 #define serial_out(x, y) out_be32(y, x) 30 #define serial_in(y) in_be32(y) 31 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0) 32 #define serial_out(x, y) out_le32(y, x) 33 #define serial_in(y) in_le32(y) 34 #else 35 #define serial_out(x, y) writeb(x, y) 36 #define serial_in(y) readb(y) 37 #endif 38 #endif /* !CONFIG_DM_SERIAL */ 39 40 #if defined(CONFIG_SOC_KEYSTONE) 41 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 42 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) 43 #undef UART_MCRVAL 44 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL 45 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) 46 #else 47 #define UART_MCRVAL (UART_MCR_RTS) 48 #endif 49 #endif 50 51 #ifndef CONFIG_SYS_NS16550_IER 52 #define CONFIG_SYS_NS16550_IER 0x00 53 #endif /* CONFIG_SYS_NS16550_IER */ 54 55 static inline void serial_out_shift(void *addr, int shift, int value) 56 { 57 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 58 outb(value, (ulong)addr); 59 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) 60 out_le32(addr, value); 61 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 62 out_be32(addr, value); 63 #elif defined(CONFIG_SYS_NS16550_MEM32) 64 writel(value, addr); 65 #elif defined(CONFIG_SYS_BIG_ENDIAN) 66 writeb(value, addr + (1 << shift) - 1); 67 #else 68 writeb(value, addr); 69 #endif 70 } 71 72 static inline int serial_in_shift(void *addr, int shift) 73 { 74 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 75 return inb((ulong)addr); 76 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) 77 return in_le32(addr); 78 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 79 return in_be32(addr); 80 #elif defined(CONFIG_SYS_NS16550_MEM32) 81 return readl(addr); 82 #elif defined(CONFIG_SYS_BIG_ENDIAN) 83 return readb(addr + (1 << shift) - 1); 84 #else 85 return readb(addr); 86 #endif 87 } 88 89 #ifdef CONFIG_DM_SERIAL 90 91 #ifndef CONFIG_SYS_NS16550_CLK 92 #define CONFIG_SYS_NS16550_CLK 0 93 #endif 94 95 static void ns16550_writeb(NS16550_t port, int offset, int value) 96 { 97 struct ns16550_platdata *plat = port->plat; 98 unsigned char *addr; 99 100 offset *= 1 << plat->reg_shift; 101 addr = (unsigned char *)plat->base + offset; 102 103 /* 104 * As far as we know it doesn't make sense to support selection of 105 * these options at run-time, so use the existing CONFIG options. 106 */ 107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); 108 } 109 110 static int ns16550_readb(NS16550_t port, int offset) 111 { 112 struct ns16550_platdata *plat = port->plat; 113 unsigned char *addr; 114 115 offset *= 1 << plat->reg_shift; 116 addr = (unsigned char *)plat->base + offset; 117 118 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); 119 } 120 121 static u32 ns16550_getfcr(NS16550_t port) 122 { 123 struct ns16550_platdata *plat = port->plat; 124 125 return plat->fcr; 126 } 127 128 /* We can clean these up once everything is moved to driver model */ 129 #define serial_out(value, addr) \ 130 ns16550_writeb(com_port, \ 131 (unsigned char *)addr - (unsigned char *)com_port, value) 132 #define serial_in(addr) \ 133 ns16550_readb(com_port, \ 134 (unsigned char *)addr - (unsigned char *)com_port) 135 #else 136 static u32 ns16550_getfcr(NS16550_t port) 137 { 138 return UART_FCR_DEFVAL; 139 } 140 #endif 141 142 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) 143 { 144 const unsigned int mode_x_div = 16; 145 146 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); 147 } 148 149 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) 150 { 151 serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); 152 serial_out(baud_divisor & 0xff, &com_port->dll); 153 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); 154 serial_out(UART_LCRVAL, &com_port->lcr); 155 } 156 157 void NS16550_init(NS16550_t com_port, int baud_divisor) 158 { 159 #if (defined(CONFIG_SPL_BUILD) && \ 160 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) 161 /* 162 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode 163 * before SPL starts only THRE bit is set. We have to empty the 164 * transmitter before initialization starts. 165 */ 166 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) 167 == UART_LSR_THRE) { 168 if (baud_divisor != -1) 169 NS16550_setbrg(com_port, baud_divisor); 170 serial_out(0, &com_port->mdr1); 171 } 172 #endif 173 174 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) 175 ; 176 177 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 178 #if defined(CONFIG_ARCH_OMAP2PLUS) 179 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ 180 #endif 181 182 serial_out(UART_MCRVAL, &com_port->mcr); 183 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 184 if (baud_divisor != -1) 185 NS16550_setbrg(com_port, baud_divisor); 186 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) 187 /* /16 is proper to hit 115200 with 48MHz */ 188 serial_out(0, &com_port->mdr1); 189 #endif 190 #if defined(CONFIG_SOC_KEYSTONE) 191 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); 192 #endif 193 } 194 195 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 196 void NS16550_reinit(NS16550_t com_port, int baud_divisor) 197 { 198 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 199 NS16550_setbrg(com_port, 0); 200 serial_out(UART_MCRVAL, &com_port->mcr); 201 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 202 NS16550_setbrg(com_port, baud_divisor); 203 } 204 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 205 206 void NS16550_putc(NS16550_t com_port, char c) 207 { 208 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) 209 ; 210 serial_out(c, &com_port->thr); 211 212 /* 213 * Call watchdog_reset() upon newline. This is done here in putc 214 * since the environment code uses a single puts() to print the complete 215 * environment upon "printenv". So we can't put this watchdog call 216 * in puts(). 217 */ 218 if (c == '\n') 219 WATCHDOG_RESET(); 220 } 221 222 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 223 char NS16550_getc(NS16550_t com_port) 224 { 225 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { 226 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY) 227 extern void usbtty_poll(void); 228 usbtty_poll(); 229 #endif 230 WATCHDOG_RESET(); 231 } 232 return serial_in(&com_port->rbr); 233 } 234 235 int NS16550_tstc(NS16550_t com_port) 236 { 237 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; 238 } 239 240 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 241 242 #ifdef CONFIG_DEBUG_UART_NS16550 243 244 #include <debug_uart.h> 245 246 static inline void _debug_uart_init(void) 247 { 248 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 249 int baud_divisor; 250 251 /* 252 * We copy the code from above because it is already horribly messy. 253 * Trying to refactor to nicely remove the duplication doesn't seem 254 * feasible. The better fix is to move all users of this driver to 255 * driver model. 256 */ 257 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, 258 CONFIG_BAUDRATE); 259 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); 260 serial_dout(&com_port->mcr, UART_MCRVAL); 261 serial_dout(&com_port->fcr, UART_FCR_DEFVAL); 262 263 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); 264 serial_dout(&com_port->dll, baud_divisor & 0xff); 265 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); 266 serial_dout(&com_port->lcr, UART_LCRVAL); 267 } 268 269 static inline void _debug_uart_putc(int ch) 270 { 271 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 272 273 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) 274 ; 275 serial_dout(&com_port->thr, ch); 276 } 277 278 DEBUG_UART_FUNCS 279 280 #endif 281 282 #ifdef CONFIG_DEBUG_UART_OMAP 283 284 #include <debug_uart.h> 285 286 static inline void _debug_uart_init(void) 287 { 288 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 289 int baud_divisor; 290 291 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, 292 CONFIG_BAUDRATE); 293 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); 294 serial_dout(&com_port->mdr1, 0x7); 295 serial_dout(&com_port->mcr, UART_MCRVAL); 296 serial_dout(&com_port->fcr, UART_FCR_DEFVAL); 297 298 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); 299 serial_dout(&com_port->dll, baud_divisor & 0xff); 300 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); 301 serial_dout(&com_port->lcr, UART_LCRVAL); 302 serial_dout(&com_port->mdr1, 0x0); 303 } 304 305 static inline void _debug_uart_putc(int ch) 306 { 307 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 308 309 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) 310 ; 311 serial_dout(&com_port->thr, ch); 312 } 313 314 DEBUG_UART_FUNCS 315 316 #endif 317 318 #ifdef CONFIG_DM_SERIAL 319 static int ns16550_serial_putc(struct udevice *dev, const char ch) 320 { 321 struct NS16550 *const com_port = dev_get_priv(dev); 322 323 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) 324 return -EAGAIN; 325 serial_out(ch, &com_port->thr); 326 327 /* 328 * Call watchdog_reset() upon newline. This is done here in putc 329 * since the environment code uses a single puts() to print the complete 330 * environment upon "printenv". So we can't put this watchdog call 331 * in puts(). 332 */ 333 if (ch == '\n') 334 WATCHDOG_RESET(); 335 336 return 0; 337 } 338 339 static int ns16550_serial_pending(struct udevice *dev, bool input) 340 { 341 struct NS16550 *const com_port = dev_get_priv(dev); 342 343 if (input) 344 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0; 345 else 346 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1; 347 } 348 349 static int ns16550_serial_getc(struct udevice *dev) 350 { 351 struct NS16550 *const com_port = dev_get_priv(dev); 352 353 if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) 354 return -EAGAIN; 355 356 return serial_in(&com_port->rbr); 357 } 358 359 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) 360 { 361 struct NS16550 *const com_port = dev_get_priv(dev); 362 struct ns16550_platdata *plat = com_port->plat; 363 int clock_divisor; 364 365 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); 366 367 NS16550_setbrg(com_port, clock_divisor); 368 369 return 0; 370 } 371 372 int ns16550_serial_probe(struct udevice *dev) 373 { 374 struct NS16550 *const com_port = dev_get_priv(dev); 375 struct reset_ctl_bulk reset_bulk; 376 int ret; 377 378 ret = reset_get_bulk(dev, &reset_bulk); 379 if (!ret) 380 reset_deassert_bulk(&reset_bulk); 381 382 com_port->plat = dev_get_platdata(dev); 383 NS16550_init(com_port, -1); 384 385 return 0; 386 } 387 388 #if CONFIG_IS_ENABLED(OF_CONTROL) 389 enum { 390 PORT_NS16550 = 0, 391 PORT_JZ4780, 392 }; 393 #endif 394 395 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 396 int ns16550_serial_ofdata_to_platdata(struct udevice *dev) 397 { 398 struct ns16550_platdata *plat = dev->platdata; 399 const u32 port_type = dev_get_driver_data(dev); 400 fdt_addr_t addr; 401 struct clk clk; 402 int err; 403 404 /* try Processor Local Bus device first */ 405 addr = dev_read_addr(dev); 406 #if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI) 407 if (addr == FDT_ADDR_T_NONE) { 408 /* then try pci device */ 409 struct fdt_pci_addr pci_addr; 410 u32 bar; 411 int ret; 412 413 /* we prefer to use a memory-mapped register */ 414 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev), 415 FDT_PCI_SPACE_MEM32, "reg", 416 &pci_addr); 417 if (ret) { 418 /* try if there is any i/o-mapped register */ 419 ret = fdtdec_get_pci_addr(gd->fdt_blob, 420 dev_of_offset(dev), 421 FDT_PCI_SPACE_IO, 422 "reg", &pci_addr); 423 if (ret) 424 return ret; 425 } 426 427 ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar); 428 if (ret) 429 return ret; 430 431 addr = bar; 432 } 433 #endif 434 435 if (addr == FDT_ADDR_T_NONE) 436 return -EINVAL; 437 438 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 439 plat->base = addr; 440 #else 441 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); 442 #endif 443 444 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); 445 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); 446 447 err = clk_get_by_index(dev, 0, &clk); 448 if (!err) { 449 err = clk_get_rate(&clk); 450 if (!IS_ERR_VALUE(err)) 451 plat->clock = err; 452 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { 453 debug("ns16550 failed to get clock\n"); 454 return err; 455 } 456 457 if (!plat->clock) 458 plat->clock = dev_read_u32_default(dev, "clock-frequency", 459 CONFIG_SYS_NS16550_CLK); 460 if (!plat->clock) { 461 debug("ns16550 clock not defined\n"); 462 return -EINVAL; 463 } 464 465 plat->fcr = UART_FCR_DEFVAL; 466 if (port_type == PORT_JZ4780) 467 plat->fcr |= UART_FCR_UME; 468 469 return 0; 470 } 471 #endif 472 473 const struct dm_serial_ops ns16550_serial_ops = { 474 .putc = ns16550_serial_putc, 475 .pending = ns16550_serial_pending, 476 .getc = ns16550_serial_getc, 477 .setbrg = ns16550_serial_setbrg, 478 }; 479 480 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 481 /* 482 * Please consider existing compatible strings before adding a new 483 * one to keep this table compact. Or you may add a generic "ns16550" 484 * compatible string to your dts. 485 */ 486 static const struct udevice_id ns16550_serial_ids[] = { 487 { .compatible = "ns16550", .data = PORT_NS16550 }, 488 { .compatible = "ns16550a", .data = PORT_NS16550 }, 489 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, 490 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, 491 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, 492 { .compatible = "ti,omap2-uart", .data = PORT_NS16550 }, 493 { .compatible = "ti,omap3-uart", .data = PORT_NS16550 }, 494 { .compatible = "ti,omap4-uart", .data = PORT_NS16550 }, 495 { .compatible = "ti,am3352-uart", .data = PORT_NS16550 }, 496 { .compatible = "ti,am4372-uart", .data = PORT_NS16550 }, 497 { .compatible = "ti,dra742-uart", .data = PORT_NS16550 }, 498 {} 499 }; 500 #endif /* OF_CONTROL && !OF_PLATDATA */ 501 502 #if CONFIG_IS_ENABLED(SERIAL_PRESENT) 503 504 /* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */ 505 #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL) 506 U_BOOT_DRIVER(ns16550_serial) = { 507 .name = "ns16550_serial", 508 .id = UCLASS_SERIAL, 509 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 510 .of_match = ns16550_serial_ids, 511 .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata, 512 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), 513 #endif 514 .priv_auto_alloc_size = sizeof(struct NS16550), 515 .probe = ns16550_serial_probe, 516 .ops = &ns16550_serial_ops, 517 .flags = DM_FLAG_PRE_RELOC, 518 }; 519 #endif 520 #endif /* SERIAL_PRESENT */ 521 522 #endif /* CONFIG_DM_SERIAL */ 523