1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. 4 * TsiChung Liew, Tsi-Chung.Liew@freescale.com. 5 * 6 * Modified to add device model (DM) support 7 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> 8 */ 9 10 /* 11 * Minimal serial functions needed to use one of the uart ports 12 * as serial console interface. 13 */ 14 15 #include <common.h> 16 #include <dm.h> 17 #include <dm/platform_data/serial_coldfire.h> 18 #include <serial.h> 19 #include <linux/compiler.h> 20 #include <asm/immap.h> 21 #include <asm/uart.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 extern void uart_port_conf(int port); 26 27 static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate) 28 { 29 u32 counter; 30 31 uart_port_conf(port_idx); 32 33 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ 34 writeb(UART_UCR_RESET_RX, &uart->ucr); 35 writeb(UART_UCR_RESET_TX, &uart->ucr); 36 writeb(UART_UCR_RESET_ERROR, &uart->ucr); 37 writeb(UART_UCR_RESET_MR, &uart->ucr); 38 __asm__("nop"); 39 40 writeb(0, &uart->uimr); 41 42 /* write to CSR: RX/TX baud rate from timers */ 43 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); 44 45 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); 46 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); 47 48 /* Setting up BaudRate */ 49 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2)); 50 counter = counter / baudrate; 51 52 /* write to CTUR: divide counter upper byte */ 53 writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1); 54 /* write to CTLR: divide counter lower byte */ 55 writeb((u8)(counter & 0x00ff), &uart->ubg2); 56 57 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); 58 59 return (0); 60 } 61 62 static void mcf_serial_setbrg_common(uart_t *uart, int baudrate) 63 { 64 u32 counter; 65 66 /* Setting up BaudRate */ 67 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2)); 68 counter = counter / baudrate; 69 70 /* write to CTUR: divide counter upper byte */ 71 writeb(((counter & 0xff00) >> 8), &uart->ubg1); 72 /* write to CTLR: divide counter lower byte */ 73 writeb((counter & 0x00ff), &uart->ubg2); 74 75 writeb(UART_UCR_RESET_RX, &uart->ucr); 76 writeb(UART_UCR_RESET_TX, &uart->ucr); 77 78 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); 79 } 80 81 #ifndef CONFIG_DM_SERIAL 82 83 static int mcf_serial_init(void) 84 { 85 uart_t *uart_base; 86 int port_idx; 87 88 uart_base = (uart_t *)CONFIG_SYS_UART_BASE; 89 port_idx = CONFIG_SYS_UART_PORT; 90 91 return mcf_serial_init_common(uart_base, port_idx, gd->baudrate); 92 } 93 94 static void mcf_serial_putc(const char c) 95 { 96 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; 97 98 if (c == '\n') 99 serial_putc('\r'); 100 101 /* Wait for last character to go. */ 102 while (!(readb(&uart->usr) & UART_USR_TXRDY)) 103 ; 104 105 writeb(c, &uart->utb); 106 } 107 108 static int mcf_serial_getc(void) 109 { 110 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; 111 112 /* Wait for a character to arrive. */ 113 while (!(readb(&uart->usr) & UART_USR_RXRDY)) 114 ; 115 116 return readb(&uart->urb); 117 } 118 119 static void mcf_serial_setbrg(void) 120 { 121 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; 122 123 mcf_serial_setbrg_common(uart, gd->baudrate); 124 } 125 126 static int mcf_serial_tstc(void) 127 { 128 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; 129 130 return readb(&uart->usr) & UART_USR_RXRDY; 131 } 132 133 static struct serial_device mcf_serial_drv = { 134 .name = "mcf_serial", 135 .start = mcf_serial_init, 136 .stop = NULL, 137 .setbrg = mcf_serial_setbrg, 138 .putc = mcf_serial_putc, 139 .puts = default_serial_puts, 140 .getc = mcf_serial_getc, 141 .tstc = mcf_serial_tstc, 142 }; 143 144 void mcf_serial_initialize(void) 145 { 146 serial_register(&mcf_serial_drv); 147 } 148 149 __weak struct serial_device *default_serial_console(void) 150 { 151 return &mcf_serial_drv; 152 } 153 154 #endif 155 156 #ifdef CONFIG_DM_SERIAL 157 158 static int coldfire_serial_probe(struct udevice *dev) 159 { 160 struct coldfire_serial_platdata *plat = dev->platdata; 161 162 return mcf_serial_init_common((uart_t *)plat->base, 163 plat->port, plat->baudrate); 164 } 165 166 static int coldfire_serial_putc(struct udevice *dev, const char ch) 167 { 168 struct coldfire_serial_platdata *plat = dev->platdata; 169 uart_t *uart = (uart_t *)plat->base; 170 171 /* Wait for last character to go. */ 172 if (!(readb(&uart->usr) & UART_USR_TXRDY)) 173 return -EAGAIN; 174 175 writeb(ch, &uart->utb); 176 177 return 0; 178 } 179 180 static int coldfire_serial_getc(struct udevice *dev) 181 { 182 struct coldfire_serial_platdata *plat = dev->platdata; 183 uart_t *uart = (uart_t *)(plat->base); 184 185 /* Wait for a character to arrive. */ 186 if (!(readb(&uart->usr) & UART_USR_RXRDY)) 187 return -EAGAIN; 188 189 return readb(&uart->urb); 190 } 191 192 int coldfire_serial_setbrg(struct udevice *dev, int baudrate) 193 { 194 struct coldfire_serial_platdata *plat = dev->platdata; 195 uart_t *uart = (uart_t *)(plat->base); 196 197 mcf_serial_setbrg_common(uart, baudrate); 198 199 return 0; 200 } 201 202 static int coldfire_serial_pending(struct udevice *dev, bool input) 203 { 204 struct coldfire_serial_platdata *plat = dev->platdata; 205 uart_t *uart = (uart_t *)(plat->base); 206 207 if (input) 208 return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0; 209 else 210 return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1; 211 212 return 0; 213 } 214 215 static const struct dm_serial_ops coldfire_serial_ops = { 216 .putc = coldfire_serial_putc, 217 .pending = coldfire_serial_pending, 218 .getc = coldfire_serial_getc, 219 .setbrg = coldfire_serial_setbrg, 220 }; 221 222 U_BOOT_DRIVER(serial_coldfire) = { 223 .name = "serial_coldfire", 224 .id = UCLASS_SERIAL, 225 .probe = coldfire_serial_probe, 226 .ops = &coldfire_serial_ops, 227 .flags = DM_FLAG_PRE_RELOC, 228 }; 229 #endif 230