1 /* 2 * (C) Copyright 2007 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * based on a the Linux rtc-x1207.c driver which is: 6 * Copyright 2004 Karen Spearel 7 * Copyright 2005 Alessandro Zummo 8 * 9 * Information and datasheet: 10 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 /* 16 * Date & Time support for Xicor/Intersil X1205 RTC 17 */ 18 19 /* #define DEBUG */ 20 21 #include <common.h> 22 #include <command.h> 23 #include <rtc.h> 24 #include <i2c.h> 25 26 #if defined(CONFIG_CMD_DATE) 27 28 #define CCR_SEC 0 29 #define CCR_MIN 1 30 #define CCR_HOUR 2 31 #define CCR_MDAY 3 32 #define CCR_MONTH 4 33 #define CCR_YEAR 5 34 #define CCR_WDAY 6 35 #define CCR_Y2K 7 36 37 #define X1205_REG_SR 0x3F /* status register */ 38 #define X1205_REG_Y2K 0x37 39 #define X1205_REG_DW 0x36 40 #define X1205_REG_YR 0x35 41 #define X1205_REG_MO 0x34 42 #define X1205_REG_DT 0x33 43 #define X1205_REG_HR 0x32 44 #define X1205_REG_MN 0x31 45 #define X1205_REG_SC 0x30 46 #define X1205_REG_DTR 0x13 47 #define X1205_REG_ATR 0x12 48 #define X1205_REG_INT 0x11 49 #define X1205_REG_0 0x10 50 #define X1205_REG_Y2K1 0x0F 51 #define X1205_REG_DWA1 0x0E 52 #define X1205_REG_YRA1 0x0D 53 #define X1205_REG_MOA1 0x0C 54 #define X1205_REG_DTA1 0x0B 55 #define X1205_REG_HRA1 0x0A 56 #define X1205_REG_MNA1 0x09 57 #define X1205_REG_SCA1 0x08 58 #define X1205_REG_Y2K0 0x07 59 #define X1205_REG_DWA0 0x06 60 #define X1205_REG_YRA0 0x05 61 #define X1205_REG_MOA0 0x04 62 #define X1205_REG_DTA0 0x03 63 #define X1205_REG_HRA0 0x02 64 #define X1205_REG_MNA0 0x01 65 #define X1205_REG_SCA0 0x00 66 67 #define X1205_CCR_BASE 0x30 /* Base address of CCR */ 68 #define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ 69 70 #define X1205_SR_RTCF 0x01 /* Clock failure */ 71 #define X1205_SR_WEL 0x02 /* Write Enable Latch */ 72 #define X1205_SR_RWEL 0x04 /* Register Write Enable */ 73 74 #define X1205_DTR_DTR0 0x01 75 #define X1205_DTR_DTR1 0x02 76 #define X1205_DTR_DTR2 0x04 77 78 #define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ 79 80 static void rtc_write(int reg, u8 val) 81 { 82 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); 83 } 84 85 /* 86 * In the routines that deal directly with the x1205 hardware, we use 87 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch 88 * Epoch is initialized as 2000. Time is set to UTC. 89 */ 90 int rtc_get(struct rtc_time *tm) 91 { 92 u8 buf[8]; 93 94 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); 95 96 debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " 97 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", 98 __FUNCTION__, 99 buf[0], buf[1], buf[2], buf[3], 100 buf[4], buf[5], buf[6], buf[7]); 101 102 tm->tm_sec = bcd2bin(buf[CCR_SEC]); 103 tm->tm_min = bcd2bin(buf[CCR_MIN]); 104 tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ 105 tm->tm_mday = bcd2bin(buf[CCR_MDAY]); 106 tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */ 107 tm->tm_year = bcd2bin(buf[CCR_YEAR]) 108 + (bcd2bin(buf[CCR_Y2K]) * 100); 109 tm->tm_wday = buf[CCR_WDAY]; 110 111 debug("%s: tm is secs=%d, mins=%d, hours=%d, " 112 "mday=%d, mon=%d, year=%d, wday=%d\n", 113 __FUNCTION__, 114 tm->tm_sec, tm->tm_min, tm->tm_hour, 115 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 116 117 return 0; 118 } 119 120 int rtc_set(struct rtc_time *tm) 121 { 122 int i; 123 u8 buf[8]; 124 125 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 126 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, 127 tm->tm_hour, tm->tm_min, tm->tm_sec); 128 129 buf[CCR_SEC] = bin2bcd(tm->tm_sec); 130 buf[CCR_MIN] = bin2bcd(tm->tm_min); 131 132 /* set hour and 24hr bit */ 133 buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL; 134 135 buf[CCR_MDAY] = bin2bcd(tm->tm_mday); 136 137 /* month, 1 - 12 */ 138 buf[CCR_MONTH] = bin2bcd(tm->tm_mon); 139 140 /* year, since the rtc epoch*/ 141 buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100); 142 buf[CCR_WDAY] = tm->tm_wday & 0x07; 143 buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100); 144 145 /* this sequence is required to unlock the chip */ 146 rtc_write(X1205_REG_SR, X1205_SR_WEL); 147 rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL); 148 149 /* write register's data */ 150 for (i = 0; i < 8; i++) 151 rtc_write(X1205_CCR_BASE + i, buf[i]); 152 153 rtc_write(X1205_REG_SR, 0); 154 155 return 0; 156 } 157 158 void rtc_reset(void) 159 { 160 /* 161 * Nothing to do 162 */ 163 } 164 165 #endif 166