1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007 4 * Stefan Roese, DENX Software Engineering, sr@denx.de. 5 * 6 * based on a the Linux rtc-x1207.c driver which is: 7 * Copyright 2004 Karen Spearel 8 * Copyright 2005 Alessandro Zummo 9 * 10 * Information and datasheet: 11 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html 12 */ 13 14 /* 15 * Date & Time support for Xicor/Intersil X1205 RTC 16 */ 17 18 /* #define DEBUG */ 19 20 #include <common.h> 21 #include <command.h> 22 #include <rtc.h> 23 #include <i2c.h> 24 25 #if defined(CONFIG_CMD_DATE) 26 27 #define CCR_SEC 0 28 #define CCR_MIN 1 29 #define CCR_HOUR 2 30 #define CCR_MDAY 3 31 #define CCR_MONTH 4 32 #define CCR_YEAR 5 33 #define CCR_WDAY 6 34 #define CCR_Y2K 7 35 36 #define X1205_REG_SR 0x3F /* status register */ 37 #define X1205_REG_Y2K 0x37 38 #define X1205_REG_DW 0x36 39 #define X1205_REG_YR 0x35 40 #define X1205_REG_MO 0x34 41 #define X1205_REG_DT 0x33 42 #define X1205_REG_HR 0x32 43 #define X1205_REG_MN 0x31 44 #define X1205_REG_SC 0x30 45 #define X1205_REG_DTR 0x13 46 #define X1205_REG_ATR 0x12 47 #define X1205_REG_INT 0x11 48 #define X1205_REG_0 0x10 49 #define X1205_REG_Y2K1 0x0F 50 #define X1205_REG_DWA1 0x0E 51 #define X1205_REG_YRA1 0x0D 52 #define X1205_REG_MOA1 0x0C 53 #define X1205_REG_DTA1 0x0B 54 #define X1205_REG_HRA1 0x0A 55 #define X1205_REG_MNA1 0x09 56 #define X1205_REG_SCA1 0x08 57 #define X1205_REG_Y2K0 0x07 58 #define X1205_REG_DWA0 0x06 59 #define X1205_REG_YRA0 0x05 60 #define X1205_REG_MOA0 0x04 61 #define X1205_REG_DTA0 0x03 62 #define X1205_REG_HRA0 0x02 63 #define X1205_REG_MNA0 0x01 64 #define X1205_REG_SCA0 0x00 65 66 #define X1205_CCR_BASE 0x30 /* Base address of CCR */ 67 #define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ 68 69 #define X1205_SR_RTCF 0x01 /* Clock failure */ 70 #define X1205_SR_WEL 0x02 /* Write Enable Latch */ 71 #define X1205_SR_RWEL 0x04 /* Register Write Enable */ 72 73 #define X1205_DTR_DTR0 0x01 74 #define X1205_DTR_DTR1 0x02 75 #define X1205_DTR_DTR2 0x04 76 77 #define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ 78 79 static void rtc_write(int reg, u8 val) 80 { 81 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); 82 } 83 84 /* 85 * In the routines that deal directly with the x1205 hardware, we use 86 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch 87 * Epoch is initialized as 2000. Time is set to UTC. 88 */ 89 int rtc_get(struct rtc_time *tm) 90 { 91 u8 buf[8]; 92 93 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); 94 95 debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " 96 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", 97 __FUNCTION__, 98 buf[0], buf[1], buf[2], buf[3], 99 buf[4], buf[5], buf[6], buf[7]); 100 101 tm->tm_sec = bcd2bin(buf[CCR_SEC]); 102 tm->tm_min = bcd2bin(buf[CCR_MIN]); 103 tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ 104 tm->tm_mday = bcd2bin(buf[CCR_MDAY]); 105 tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */ 106 tm->tm_year = bcd2bin(buf[CCR_YEAR]) 107 + (bcd2bin(buf[CCR_Y2K]) * 100); 108 tm->tm_wday = buf[CCR_WDAY]; 109 110 debug("%s: tm is secs=%d, mins=%d, hours=%d, " 111 "mday=%d, mon=%d, year=%d, wday=%d\n", 112 __FUNCTION__, 113 tm->tm_sec, tm->tm_min, tm->tm_hour, 114 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 115 116 return 0; 117 } 118 119 int rtc_set(struct rtc_time *tm) 120 { 121 int i; 122 u8 buf[8]; 123 124 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 125 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, 126 tm->tm_hour, tm->tm_min, tm->tm_sec); 127 128 buf[CCR_SEC] = bin2bcd(tm->tm_sec); 129 buf[CCR_MIN] = bin2bcd(tm->tm_min); 130 131 /* set hour and 24hr bit */ 132 buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL; 133 134 buf[CCR_MDAY] = bin2bcd(tm->tm_mday); 135 136 /* month, 1 - 12 */ 137 buf[CCR_MONTH] = bin2bcd(tm->tm_mon); 138 139 /* year, since the rtc epoch*/ 140 buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100); 141 buf[CCR_WDAY] = tm->tm_wday & 0x07; 142 buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100); 143 144 /* this sequence is required to unlock the chip */ 145 rtc_write(X1205_REG_SR, X1205_SR_WEL); 146 rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL); 147 148 /* write register's data */ 149 for (i = 0; i < 8; i++) 150 rtc_write(X1205_CCR_BASE + i, buf[i]); 151 152 rtc_write(X1205_REG_SR, 0); 153 154 return 0; 155 } 156 157 void rtc_reset(void) 158 { 159 /* 160 * Nothing to do 161 */ 162 } 163 164 #endif 165