1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2018 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. 5 * 6 * (C) Copyright 2008 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * based on a the Linux rtc-m41t80.c driver which is: 10 * Alexander Bigga <ab@mycable.de>, 2006 (c) mycable GmbH 11 */ 12 13 /* 14 * Date & Time support for STMicroelectronics M41T62 15 */ 16 17 /* #define DEBUG */ 18 19 #include <common.h> 20 #include <command.h> 21 #include <dm.h> 22 #include <rtc.h> 23 #include <i2c.h> 24 25 #define M41T62_REG_SSEC 0 26 #define M41T62_REG_SEC 1 27 #define M41T62_REG_MIN 2 28 #define M41T62_REG_HOUR 3 29 #define M41T62_REG_WDAY 4 30 #define M41T62_REG_DAY 5 31 #define M41T62_REG_MON 6 32 #define M41T62_REG_YEAR 7 33 #define M41T62_REG_ALARM_MON 0xa 34 #define M41T62_REG_ALARM_DAY 0xb 35 #define M41T62_REG_ALARM_HOUR 0xc 36 #define M41T62_REG_ALARM_MIN 0xd 37 #define M41T62_REG_ALARM_SEC 0xe 38 #define M41T62_REG_FLAGS 0xf 39 40 #define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1) 41 #define M41T62_ALARM_REG_SIZE \ 42 (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON) 43 44 #define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */ 45 #define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */ 46 #define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */ 47 #define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ 48 #define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */ 49 #define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */ 50 51 #define M41T62_FEATURE_HT (1 << 0) 52 #define M41T62_FEATURE_BL (1 << 1) 53 54 #define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ 55 56 static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) 57 { 58 debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " 59 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", 60 __FUNCTION__, 61 buf[0], buf[1], buf[2], buf[3], 62 buf[4], buf[5], buf[6], buf[7]); 63 64 tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f); 65 tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f); 66 tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f); 67 tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f); 68 tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07; 69 tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f); 70 71 /* assume 20YY not 19YY, and ignore the Century Bit */ 72 /* U-Boot needs to add 1900 here */ 73 tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900; 74 75 debug("%s: tm is secs=%d, mins=%d, hours=%d, " 76 "mday=%d, mon=%d, year=%d, wday=%d\n", 77 __FUNCTION__, 78 tm->tm_sec, tm->tm_min, tm->tm_hour, 79 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 80 } 81 82 static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf) 83 { 84 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 85 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, 86 tm->tm_hour, tm->tm_min, tm->tm_sec); 87 88 /* Merge time-data and register flags into buf[0..7] */ 89 buf[M41T62_REG_SSEC] = 0; 90 buf[M41T62_REG_SEC] = 91 bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f); 92 buf[M41T62_REG_MIN] = 93 bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f); 94 buf[M41T62_REG_HOUR] = 95 bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ; 96 buf[M41T62_REG_WDAY] = 97 (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07); 98 buf[M41T62_REG_DAY] = 99 bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f); 100 buf[M41T62_REG_MON] = 101 bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f); 102 /* assume 20YY not 19YY */ 103 buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100); 104 } 105 106 #ifdef CONFIG_DM_RTC 107 static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm) 108 { 109 u8 buf[M41T62_DATETIME_REG_SIZE]; 110 int ret; 111 112 ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); 113 if (ret) 114 return ret; 115 116 m41t62_update_rtc_time(tm, buf); 117 118 return 0; 119 } 120 121 static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm) 122 { 123 u8 buf[M41T62_DATETIME_REG_SIZE]; 124 int ret; 125 126 ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); 127 if (ret) 128 return ret; 129 130 m41t62_set_rtc_buf(tm, buf); 131 132 ret = dm_i2c_write(dev, 0, buf, sizeof(buf)); 133 if (ret) { 134 printf("I2C write failed in %s()\n", __func__); 135 return ret; 136 } 137 138 return 0; 139 } 140 141 static int m41t62_rtc_reset(struct udevice *dev) 142 { 143 u8 val; 144 145 /* 146 * M41T82: Make sure HT (Halt Update) bit is cleared. 147 * This bit is 0 in M41T62 so its save to clear it always. 148 */ 149 150 int ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); 151 152 val &= ~M41T80_ALHOUR_HT; 153 ret |= dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); 154 155 return ret; 156 } 157 158 static const struct rtc_ops m41t62_rtc_ops = { 159 .get = m41t62_rtc_get, 160 .set = m41t62_rtc_set, 161 .reset = m41t62_rtc_reset, 162 }; 163 164 static const struct udevice_id m41t62_rtc_ids[] = { 165 { .compatible = "st,m41t62" }, 166 { .compatible = "microcrystal,rv4162" }, 167 { } 168 }; 169 170 U_BOOT_DRIVER(rtc_m41t62) = { 171 .name = "rtc-m41t62", 172 .id = UCLASS_RTC, 173 .of_match = m41t62_rtc_ids, 174 .ops = &m41t62_rtc_ops, 175 }; 176 177 #else /* NON DM RTC code - will be removed */ 178 int rtc_get(struct rtc_time *tm) 179 { 180 u8 buf[M41T62_DATETIME_REG_SIZE]; 181 182 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); 183 m41t62_update_rtc_time(tm, buf); 184 185 return 0; 186 } 187 188 int rtc_set(struct rtc_time *tm) 189 { 190 u8 buf[M41T62_DATETIME_REG_SIZE]; 191 192 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); 193 m41t62_set_rtc_buf(tm, buf); 194 195 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, 196 M41T62_DATETIME_REG_SIZE)) { 197 printf("I2C write failed in %s()\n", __func__); 198 return -1; 199 } 200 201 return 0; 202 } 203 204 void rtc_reset(void) 205 { 206 u8 val; 207 208 /* 209 * M41T82: Make sure HT (Halt Update) bit is cleared. 210 * This bit is 0 in M41T62 so its save to clear it always. 211 */ 212 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); 213 val &= ~M41T80_ALHOUR_HT; 214 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); 215 } 216 #endif /* CONFIG_DM_RTC */ 217