xref: /openbmc/u-boot/drivers/rtc/m41t62.c (revision bcc05c7a)
1 /*
2  * (C) Copyright 2008
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * based on a the Linux rtc-m41t80.c driver which is:
6  *   Alexander Bigga <ab@mycable.de>, 2006 (c) mycable GmbH
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 /*
12  * Date & Time support for STMicroelectronics M41T62
13  */
14 
15 /* #define	DEBUG	*/
16 
17 #include <common.h>
18 #include <command.h>
19 #include <rtc.h>
20 #include <i2c.h>
21 
22 #if defined(CONFIG_CMD_DATE)
23 
24 #define M41T62_REG_SSEC	0
25 #define M41T62_REG_SEC	1
26 #define M41T62_REG_MIN	2
27 #define M41T62_REG_HOUR	3
28 #define M41T62_REG_WDAY	4
29 #define M41T62_REG_DAY	5
30 #define M41T62_REG_MON	6
31 #define M41T62_REG_YEAR	7
32 #define M41T62_REG_ALARM_MON	0xa
33 #define M41T62_REG_ALARM_DAY	0xb
34 #define M41T62_REG_ALARM_HOUR	0xc
35 #define M41T62_REG_ALARM_MIN	0xd
36 #define M41T62_REG_ALARM_SEC	0xe
37 #define M41T62_REG_FLAGS	0xf
38 
39 #define M41T62_DATETIME_REG_SIZE	(M41T62_REG_YEAR + 1)
40 #define M41T62_ALARM_REG_SIZE	\
41 	(M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON)
42 
43 #define M41T62_SEC_ST		(1 << 7)	/* ST: Stop Bit */
44 #define M41T62_ALMON_AFE	(1 << 7)	/* AFE: AF Enable Bit */
45 #define M41T62_ALMON_SQWE	(1 << 6)	/* SQWE: SQW Enable Bit */
46 #define M41T62_ALHOUR_HT	(1 << 6)	/* HT: Halt Update Bit */
47 #define M41T62_FLAGS_AF		(1 << 6)	/* AF: Alarm Flag Bit */
48 #define M41T62_FLAGS_BATT_LOW	(1 << 4)	/* BL: Battery Low Bit */
49 
50 #define M41T62_FEATURE_HT	(1 << 0)
51 #define M41T62_FEATURE_BL	(1 << 1)
52 
53 #define M41T80_ALHOUR_HT	(1 << 6)	/* HT: Halt Update Bit */
54 
55 int rtc_get(struct rtc_time *tm)
56 {
57 	u8 buf[M41T62_DATETIME_REG_SIZE];
58 
59 	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
60 
61 	debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
62 	      "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
63 	      __FUNCTION__,
64 	      buf[0], buf[1], buf[2], buf[3],
65 	      buf[4], buf[5], buf[6], buf[7]);
66 
67 	tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f);
68 	tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f);
69 	tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f);
70 	tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f);
71 	tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
72 	tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f);
73 
74 	/* assume 20YY not 19YY, and ignore the Century Bit */
75 	/* U-Boot needs to add 1900 here */
76 	tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900;
77 
78 	debug("%s: tm is secs=%d, mins=%d, hours=%d, "
79 	      "mday=%d, mon=%d, year=%d, wday=%d\n",
80 	      __FUNCTION__,
81 	      tm->tm_sec, tm->tm_min, tm->tm_hour,
82 	      tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
83 
84 	return 0;
85 }
86 
87 int rtc_set(struct rtc_time *tm)
88 {
89 	u8 buf[M41T62_DATETIME_REG_SIZE];
90 
91 	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
92 	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
93 	      tm->tm_hour, tm->tm_min, tm->tm_sec);
94 
95 	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
96 
97 	/* Merge time-data and register flags into buf[0..7] */
98 	buf[M41T62_REG_SSEC] = 0;
99 	buf[M41T62_REG_SEC] =
100 		bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f);
101 	buf[M41T62_REG_MIN] =
102 		bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f);
103 	buf[M41T62_REG_HOUR] =
104 		bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ;
105 	buf[M41T62_REG_WDAY] =
106 		(tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07);
107 	buf[M41T62_REG_DAY] =
108 		bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
109 	buf[M41T62_REG_MON] =
110 		bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
111 	/* assume 20YY not 19YY */
112 	buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
113 
114 	if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) {
115 		printf("I2C write failed in %s()\n", __func__);
116 		return -1;
117 	}
118 
119 	return 0;
120 }
121 
122 void rtc_reset(void)
123 {
124 	u8 val;
125 
126 	/*
127 	 * M41T82: Make sure HT (Halt Update) bit is cleared.
128 	 * This bit is 0 in M41T62 so its save to clear it always.
129 	 */
130 	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
131 	val &= ~M41T80_ALHOUR_HT;
132 	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
133 }
134 
135 #endif
136