10c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 20c698dcaSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2001, 2002, 2003 30c698dcaSJean-Christophe PLAGNIOL-VILLARD * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 40c698dcaSJean-Christophe PLAGNIOL-VILLARD * Keith Outwater, keith_outwater@mvis.com` 50c698dcaSJean-Christophe PLAGNIOL-VILLARD * Steven Scholz, steven.scholz@imc-berlin.de 60c698dcaSJean-Christophe PLAGNIOL-VILLARD * 70c698dcaSJean-Christophe PLAGNIOL-VILLARD * See file CREDITS for list of people who contributed to this 80c698dcaSJean-Christophe PLAGNIOL-VILLARD * project. 90c698dcaSJean-Christophe PLAGNIOL-VILLARD * 100c698dcaSJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 110c698dcaSJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 120c698dcaSJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 130c698dcaSJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 140c698dcaSJean-Christophe PLAGNIOL-VILLARD * 150c698dcaSJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 160c698dcaSJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 170c698dcaSJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 180c698dcaSJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 190c698dcaSJean-Christophe PLAGNIOL-VILLARD * 200c698dcaSJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 210c698dcaSJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 220c698dcaSJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 230c698dcaSJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 240c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 250c698dcaSJean-Christophe PLAGNIOL-VILLARD 260c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 270c698dcaSJean-Christophe PLAGNIOL-VILLARD * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) 280c698dcaSJean-Christophe PLAGNIOL-VILLARD * DS1374 Real Time Clock (RTC). 290c698dcaSJean-Christophe PLAGNIOL-VILLARD * 300c698dcaSJean-Christophe PLAGNIOL-VILLARD * based on ds1337.c 310c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 320c698dcaSJean-Christophe PLAGNIOL-VILLARD 330c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <common.h> 340c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <command.h> 350c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <rtc.h> 360c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <i2c.h> 370c698dcaSJean-Christophe PLAGNIOL-VILLARD 38*871c18ddSMichal Simek #if defined(CONFIG_CMD_DATE) 390c698dcaSJean-Christophe PLAGNIOL-VILLARD 400c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/ 410c698dcaSJean-Christophe PLAGNIOL-VILLARD #undef DEBUG_RTC 420c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUG_RTC 430c698dcaSJean-Christophe PLAGNIOL-VILLARD 440c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG_RTC 450c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...) printf(fmt ,##args) 460c698dcaSJean-Christophe PLAGNIOL-VILLARD #else 470c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...) 480c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 490c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/ 500c698dcaSJean-Christophe PLAGNIOL-VILLARD 510c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifndef CFG_I2C_RTC_ADDR 520c698dcaSJean-Christophe PLAGNIOL-VILLARD # define CFG_I2C_RTC_ADDR 0x68 530c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 540c698dcaSJean-Christophe PLAGNIOL-VILLARD 550c698dcaSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_RTC_DS1374) && (CFG_I2C_SPEED > 400000) 560c698dcaSJean-Christophe PLAGNIOL-VILLARD # error The DS1374 is specified up to 400kHz in fast mode! 570c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 580c698dcaSJean-Christophe PLAGNIOL-VILLARD 590c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 600c698dcaSJean-Christophe PLAGNIOL-VILLARD * RTC register addresses 610c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 620c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */ 630c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE1_ADDR 0x01 640c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE2_ADDR 0x02 650c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE3_ADDR 0x03 660c698dcaSJean-Christophe PLAGNIOL-VILLARD 670c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04 680c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05 690c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06 700c698dcaSJean-Christophe PLAGNIOL-VILLARD 710c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */ 720c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */ 730c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */ 740c698dcaSJean-Christophe PLAGNIOL-VILLARD 750c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */ 760c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */ 770c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */ 780c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */ 790c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */ 800c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */ 810c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/ 820c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */ 830c698dcaSJean-Christophe PLAGNIOL-VILLARD 840c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */ 850c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */ 860c698dcaSJean-Christophe PLAGNIOL-VILLARD 870c698dcaSJean-Christophe PLAGNIOL-VILLARD typedef unsigned char boolean_t; 880c698dcaSJean-Christophe PLAGNIOL-VILLARD 890c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifndef TRUE 900c698dcaSJean-Christophe PLAGNIOL-VILLARD #define TRUE ((boolean_t)(0==0)) 910c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 920c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifndef FALSE 930c698dcaSJean-Christophe PLAGNIOL-VILLARD #define FALSE (!TRUE) 940c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 950c698dcaSJean-Christophe PLAGNIOL-VILLARD 960c698dcaSJean-Christophe PLAGNIOL-VILLARD const char RtcTodAddr[] = { 970c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE0_ADDR, 980c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE1_ADDR, 990c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE2_ADDR, 1000c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE3_ADDR 1010c698dcaSJean-Christophe PLAGNIOL-VILLARD }; 1020c698dcaSJean-Christophe PLAGNIOL-VILLARD 1030c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg); 1040c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val, boolean_t set); 1050c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write_raw (uchar reg, uchar val); 1060c698dcaSJean-Christophe PLAGNIOL-VILLARD 1070c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 1080c698dcaSJean-Christophe PLAGNIOL-VILLARD * Get the current time from the RTC 1090c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 110b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tm){ 111b73a19e1SYuri Tikhonov int rel = 0; 1120c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned long time1, time2; 1130c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned int limit; 1140c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned char tmp; 1150c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned int i; 1160c698dcaSJean-Christophe PLAGNIOL-VILLARD 1170c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 1180c698dcaSJean-Christophe PLAGNIOL-VILLARD * Since the reads are being performed one byte at a time, 1190c698dcaSJean-Christophe PLAGNIOL-VILLARD * there is a chance that a carry will occur during the read. 1200c698dcaSJean-Christophe PLAGNIOL-VILLARD * To detect this, 2 reads are performed and compared. 1210c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 1220c698dcaSJean-Christophe PLAGNIOL-VILLARD limit = 10; 1230c698dcaSJean-Christophe PLAGNIOL-VILLARD do { 1240c698dcaSJean-Christophe PLAGNIOL-VILLARD i = 4; 1250c698dcaSJean-Christophe PLAGNIOL-VILLARD time1 = 0; 1260c698dcaSJean-Christophe PLAGNIOL-VILLARD while (i--) { 1270c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp = rtc_read(RtcTodAddr[i]); 1280c698dcaSJean-Christophe PLAGNIOL-VILLARD time1 = (time1 << 8) | (tmp & 0xff); 1290c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1300c698dcaSJean-Christophe PLAGNIOL-VILLARD 1310c698dcaSJean-Christophe PLAGNIOL-VILLARD i = 4; 1320c698dcaSJean-Christophe PLAGNIOL-VILLARD time2 = 0; 1330c698dcaSJean-Christophe PLAGNIOL-VILLARD while (i--) { 1340c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp = rtc_read(RtcTodAddr[i]); 1350c698dcaSJean-Christophe PLAGNIOL-VILLARD time2 = (time2 << 8) | (tmp & 0xff); 1360c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1370c698dcaSJean-Christophe PLAGNIOL-VILLARD } while ((time1 != time2) && limit--); 1380c698dcaSJean-Christophe PLAGNIOL-VILLARD 1390c698dcaSJean-Christophe PLAGNIOL-VILLARD if (time1 != time2) { 1400c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("can't get consistent time from rtc chip\n"); 141b73a19e1SYuri Tikhonov rel = -1; 1420c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1430c698dcaSJean-Christophe PLAGNIOL-VILLARD 1444109df6fSKim Phillips DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1); 1450c698dcaSJean-Christophe PLAGNIOL-VILLARD 1460c698dcaSJean-Christophe PLAGNIOL-VILLARD to_tm(time1, tm); /* To Gregorian Date */ 1470c698dcaSJean-Christophe PLAGNIOL-VILLARD 148b73a19e1SYuri Tikhonov if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) { 1490c698dcaSJean-Christophe PLAGNIOL-VILLARD printf ("### Warning: RTC oscillator has stopped\n"); 150b73a19e1SYuri Tikhonov rel = -1; 151b73a19e1SYuri Tikhonov } 1520c698dcaSJean-Christophe PLAGNIOL-VILLARD 1530c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 1540c698dcaSJean-Christophe PLAGNIOL-VILLARD tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, 1550c698dcaSJean-Christophe PLAGNIOL-VILLARD tm->tm_hour, tm->tm_min, tm->tm_sec); 156b73a19e1SYuri Tikhonov 157b73a19e1SYuri Tikhonov return rel; 1580c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1590c698dcaSJean-Christophe PLAGNIOL-VILLARD 1600c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 1610c698dcaSJean-Christophe PLAGNIOL-VILLARD * Set the RTC 1620c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 1630c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_set (struct rtc_time *tmp){ 1640c698dcaSJean-Christophe PLAGNIOL-VILLARD 1650c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned long time; 1660c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned i; 1670c698dcaSJean-Christophe PLAGNIOL-VILLARD 1680c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 1690c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, 1700c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour, tmp->tm_min, tmp->tm_sec); 1710c698dcaSJean-Christophe PLAGNIOL-VILLARD 1720c698dcaSJean-Christophe PLAGNIOL-VILLARD if (tmp->tm_year < 1970 || tmp->tm_year > 2069) 1730c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("WARNING: year should be between 1970 and 2069!\n"); 1740c698dcaSJean-Christophe PLAGNIOL-VILLARD 1750c698dcaSJean-Christophe PLAGNIOL-VILLARD time = mktime(tmp->tm_year, tmp->tm_mon, 1760c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_mday, tmp->tm_hour, 1770c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_min, tmp->tm_sec); 1780c698dcaSJean-Christophe PLAGNIOL-VILLARD 1794109df6fSKim Phillips DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time); 1800c698dcaSJean-Christophe PLAGNIOL-VILLARD 1810c698dcaSJean-Christophe PLAGNIOL-VILLARD /* write to RTC_TOD_CNT_BYTEn_ADDR */ 1820c698dcaSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i <= 3; i++) { 1830c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff)); 1840c698dcaSJean-Christophe PLAGNIOL-VILLARD time = time >> 8; 1850c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1860c698dcaSJean-Christophe PLAGNIOL-VILLARD 1870c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Start clock */ 1880c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE); 1890c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1900c698dcaSJean-Christophe PLAGNIOL-VILLARD 1910c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 1920c698dcaSJean-Christophe PLAGNIOL-VILLARD * Reset the RTC. We setting the date back to 1970-01-01. 1930c698dcaSJean-Christophe PLAGNIOL-VILLARD * We also enable the oscillator output on the SQW/OUT pin and program 1940c698dcaSJean-Christophe PLAGNIOL-VILLARD * it for 32,768 Hz output. Note that according to the datasheet, turning 1950c698dcaSJean-Christophe PLAGNIOL-VILLARD * on the square wave output increases the current drain on the backup 1960c698dcaSJean-Christophe PLAGNIOL-VILLARD * battery to something between 480nA and 800nA. 1970c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 1980c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void){ 1990c698dcaSJean-Christophe PLAGNIOL-VILLARD 2000c698dcaSJean-Christophe PLAGNIOL-VILLARD struct rtc_time tmp; 2010c698dcaSJean-Christophe PLAGNIOL-VILLARD 2020c698dcaSJean-Christophe PLAGNIOL-VILLARD /* clear status flags */ 2030c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */ 2040c698dcaSJean-Christophe PLAGNIOL-VILLARD 2050c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Initialise DS1374 oriented to MPC8349E-ADS */ 2060c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC 2070c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_WACE 2080c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE 2090c698dcaSJean-Christophe PLAGNIOL-VILLARD - set to 0 */ 2100c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM 2110c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_WDSTR 2120c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_RS1 2130c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_RS2 2140c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin, 2150c698dcaSJean-Christophe PLAGNIOL-VILLARD set BBSQW and SQW to 32k 2160c698dcaSJean-Christophe PLAGNIOL-VILLARD - set to 1 */ 2170c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year = 1970; 2180c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mon = 1; 2190c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mday= 1; 2200c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour = 0; 2210c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_min = 0; 2220c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_sec = 0; 2230c698dcaSJean-Christophe PLAGNIOL-VILLARD 2240c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_set(&tmp); 2250c698dcaSJean-Christophe PLAGNIOL-VILLARD 2260c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", 2270c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year, tmp.tm_mon, tmp.tm_mday, 2280c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour, tmp.tm_min, tmp.tm_sec); 2290c698dcaSJean-Christophe PLAGNIOL-VILLARD 2300c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE); 2310c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE); 2320c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE); 2330c698dcaSJean-Christophe PLAGNIOL-VILLARD } 2340c698dcaSJean-Christophe PLAGNIOL-VILLARD 2350c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 2360c698dcaSJean-Christophe PLAGNIOL-VILLARD * Helper functions 2370c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 2380c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg) 2390c698dcaSJean-Christophe PLAGNIOL-VILLARD { 2400c698dcaSJean-Christophe PLAGNIOL-VILLARD return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); 2410c698dcaSJean-Christophe PLAGNIOL-VILLARD } 2420c698dcaSJean-Christophe PLAGNIOL-VILLARD 2430c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val, boolean_t set) 2440c698dcaSJean-Christophe PLAGNIOL-VILLARD { 2450c698dcaSJean-Christophe PLAGNIOL-VILLARD if (set == TRUE) { 2460c698dcaSJean-Christophe PLAGNIOL-VILLARD val |= i2c_reg_read (CFG_I2C_RTC_ADDR, reg); 2470c698dcaSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); 2480c698dcaSJean-Christophe PLAGNIOL-VILLARD } else { 2490c698dcaSJean-Christophe PLAGNIOL-VILLARD val = i2c_reg_read (CFG_I2C_RTC_ADDR, reg) & ~val; 2500c698dcaSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); 2510c698dcaSJean-Christophe PLAGNIOL-VILLARD } 2520c698dcaSJean-Christophe PLAGNIOL-VILLARD } 2530c698dcaSJean-Christophe PLAGNIOL-VILLARD 2540c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write_raw (uchar reg, uchar val) 2550c698dcaSJean-Christophe PLAGNIOL-VILLARD { 2560c698dcaSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); 2570c698dcaSJean-Christophe PLAGNIOL-VILLARD } 2580c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 259