1*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 2*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2001, 2002, 2003 3*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Keith Outwater, keith_outwater@mvis.com` 5*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Steven Scholz, steven.scholz@imc-berlin.de 6*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * 7*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * See file CREDITS for list of people who contributed to this 8*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * project. 9*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * 10*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 11*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 12*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 13*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 14*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * 15*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 16*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 19*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * 20*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 21*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 22*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 24*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 25*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 26*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 27*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) 28*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * DS1374 Real Time Clock (RTC). 29*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * 30*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * based on ds1337.c 31*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 32*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 33*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <common.h> 34*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <command.h> 35*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <rtc.h> 36*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <i2c.h> 37*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 38*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #if (defined(CONFIG_RTC_DS1374)) && defined(CONFIG_CMD_DATE) 39*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 40*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/ 41*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #undef DEBUG_RTC 42*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUG_RTC 43*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 44*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG_RTC 45*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...) printf(fmt ,##args) 46*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #else 47*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...) 48*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 49*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/ 50*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 51*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifndef CFG_I2C_RTC_ADDR 52*0c698dcaSJean-Christophe PLAGNIOL-VILLARD # define CFG_I2C_RTC_ADDR 0x68 53*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 54*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 55*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_RTC_DS1374) && (CFG_I2C_SPEED > 400000) 56*0c698dcaSJean-Christophe PLAGNIOL-VILLARD # error The DS1374 is specified up to 400kHz in fast mode! 57*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 58*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 59*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 60*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * RTC register addresses 61*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 62*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */ 63*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE1_ADDR 0x01 64*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE2_ADDR 0x02 65*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE3_ADDR 0x03 66*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 67*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04 68*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05 69*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06 70*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 71*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */ 72*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */ 73*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */ 74*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 75*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */ 76*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */ 77*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */ 78*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */ 79*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */ 80*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */ 81*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/ 82*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */ 83*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 84*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */ 85*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */ 86*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 87*0c698dcaSJean-Christophe PLAGNIOL-VILLARD typedef unsigned char boolean_t; 88*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 89*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifndef TRUE 90*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define TRUE ((boolean_t)(0==0)) 91*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 92*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifndef FALSE 93*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #define FALSE (!TRUE) 94*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 95*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 96*0c698dcaSJean-Christophe PLAGNIOL-VILLARD const char RtcTodAddr[] = { 97*0c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE0_ADDR, 98*0c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE1_ADDR, 99*0c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE2_ADDR, 100*0c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE3_ADDR 101*0c698dcaSJean-Christophe PLAGNIOL-VILLARD }; 102*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 103*0c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg); 104*0c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val, boolean_t set); 105*0c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write_raw (uchar reg, uchar val); 106*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 107*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 108*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Get the current time from the RTC 109*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 110*0c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_get (struct rtc_time *tm){ 111*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 112*0c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned long time1, time2; 113*0c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned int limit; 114*0c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned char tmp; 115*0c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned int i; 116*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 117*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 118*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Since the reads are being performed one byte at a time, 119*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * there is a chance that a carry will occur during the read. 120*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * To detect this, 2 reads are performed and compared. 121*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 122*0c698dcaSJean-Christophe PLAGNIOL-VILLARD limit = 10; 123*0c698dcaSJean-Christophe PLAGNIOL-VILLARD do { 124*0c698dcaSJean-Christophe PLAGNIOL-VILLARD i = 4; 125*0c698dcaSJean-Christophe PLAGNIOL-VILLARD time1 = 0; 126*0c698dcaSJean-Christophe PLAGNIOL-VILLARD while (i--) { 127*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp = rtc_read(RtcTodAddr[i]); 128*0c698dcaSJean-Christophe PLAGNIOL-VILLARD time1 = (time1 << 8) | (tmp & 0xff); 129*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 130*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 131*0c698dcaSJean-Christophe PLAGNIOL-VILLARD i = 4; 132*0c698dcaSJean-Christophe PLAGNIOL-VILLARD time2 = 0; 133*0c698dcaSJean-Christophe PLAGNIOL-VILLARD while (i--) { 134*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp = rtc_read(RtcTodAddr[i]); 135*0c698dcaSJean-Christophe PLAGNIOL-VILLARD time2 = (time2 << 8) | (tmp & 0xff); 136*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 137*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } while ((time1 != time2) && limit--); 138*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 139*0c698dcaSJean-Christophe PLAGNIOL-VILLARD if (time1 != time2) { 140*0c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("can't get consistent time from rtc chip\n"); 141*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 142*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 143*0c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Get RTC s since 1.1.1970: %d\n", time1); 144*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 145*0c698dcaSJean-Christophe PLAGNIOL-VILLARD to_tm(time1, tm); /* To Gregorian Date */ 146*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 147*0c698dcaSJean-Christophe PLAGNIOL-VILLARD if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) 148*0c698dcaSJean-Christophe PLAGNIOL-VILLARD printf ("### Warning: RTC oscillator has stopped\n"); 149*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 150*0c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 151*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, 152*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tm->tm_hour, tm->tm_min, tm->tm_sec); 153*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 154*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 155*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 156*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Set the RTC 157*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 158*0c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_set (struct rtc_time *tmp){ 159*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 160*0c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned long time; 161*0c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned i; 162*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 163*0c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 164*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, 165*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour, tmp->tm_min, tmp->tm_sec); 166*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 167*0c698dcaSJean-Christophe PLAGNIOL-VILLARD if (tmp->tm_year < 1970 || tmp->tm_year > 2069) 168*0c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("WARNING: year should be between 1970 and 2069!\n"); 169*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 170*0c698dcaSJean-Christophe PLAGNIOL-VILLARD time = mktime(tmp->tm_year, tmp->tm_mon, 171*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_mday, tmp->tm_hour, 172*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_min, tmp->tm_sec); 173*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 174*0c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Set RTC s since 1.1.1970: %d (0x%02x)\n", time, time); 175*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 176*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* write to RTC_TOD_CNT_BYTEn_ADDR */ 177*0c698dcaSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i <= 3; i++) { 178*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff)); 179*0c698dcaSJean-Christophe PLAGNIOL-VILLARD time = time >> 8; 180*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 181*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 182*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Start clock */ 183*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE); 184*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 185*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 186*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 187*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Reset the RTC. We setting the date back to 1970-01-01. 188*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * We also enable the oscillator output on the SQW/OUT pin and program 189*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * it for 32,768 Hz output. Note that according to the datasheet, turning 190*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * on the square wave output increases the current drain on the backup 191*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * battery to something between 480nA and 800nA. 192*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 193*0c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void){ 194*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 195*0c698dcaSJean-Christophe PLAGNIOL-VILLARD struct rtc_time tmp; 196*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 197*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* clear status flags */ 198*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */ 199*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 200*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Initialise DS1374 oriented to MPC8349E-ADS */ 201*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC 202*0c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_WACE 203*0c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE 204*0c698dcaSJean-Christophe PLAGNIOL-VILLARD - set to 0 */ 205*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM 206*0c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_WDSTR 207*0c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_RS1 208*0c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_RS2 209*0c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin, 210*0c698dcaSJean-Christophe PLAGNIOL-VILLARD set BBSQW and SQW to 32k 211*0c698dcaSJean-Christophe PLAGNIOL-VILLARD - set to 1 */ 212*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year = 1970; 213*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mon = 1; 214*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mday= 1; 215*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour = 0; 216*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_min = 0; 217*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_sec = 0; 218*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 219*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_set(&tmp); 220*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 221*0c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", 222*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year, tmp.tm_mon, tmp.tm_mday, 223*0c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour, tmp.tm_min, tmp.tm_sec); 224*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 225*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE); 226*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE); 227*0c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE); 228*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 229*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 230*0c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 231*0c698dcaSJean-Christophe PLAGNIOL-VILLARD * Helper functions 232*0c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 233*0c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg) 234*0c698dcaSJean-Christophe PLAGNIOL-VILLARD { 235*0c698dcaSJean-Christophe PLAGNIOL-VILLARD return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); 236*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 237*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 238*0c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val, boolean_t set) 239*0c698dcaSJean-Christophe PLAGNIOL-VILLARD { 240*0c698dcaSJean-Christophe PLAGNIOL-VILLARD if (set == TRUE) { 241*0c698dcaSJean-Christophe PLAGNIOL-VILLARD val |= i2c_reg_read (CFG_I2C_RTC_ADDR, reg); 242*0c698dcaSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); 243*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } else { 244*0c698dcaSJean-Christophe PLAGNIOL-VILLARD val = i2c_reg_read (CFG_I2C_RTC_ADDR, reg) & ~val; 245*0c698dcaSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); 246*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 247*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 248*0c698dcaSJean-Christophe PLAGNIOL-VILLARD 249*0c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write_raw (uchar reg, uchar val) 250*0c698dcaSJean-Christophe PLAGNIOL-VILLARD { 251*0c698dcaSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); 252*0c698dcaSJean-Christophe PLAGNIOL-VILLARD } 253*0c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 254