xref: /openbmc/u-boot/drivers/rtc/at91sam9_rtt.c (revision 5c8fd32b)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2010
4  * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
5  */
6 
7 /*
8  * Date & Time support for the internal Real-time Timer
9  * of AT91SAM9260 and compatibles.
10  * Compatible with the LinuX rtc driver workaround:
11  * The RTT cannot be written to, but only reset.
12  * The actual time is the sum of RTT and one of
13  * the four GPBR registers.
14  *
15  * The at91sam9260 has 4 GPBR (0-3).
16  * For their typical use see at91_gpbr.h !
17  *
18  * make sure u-boot and kernel use the same GPBR !
19  */
20 
21 #include <common.h>
22 #include <command.h>
23 #include <rtc.h>
24 #include <asm/io.h>
25 #include <linux/errno.h>
26 #include <asm/arch/hardware.h>
27 #include <asm/arch/at91_rtt.h>
28 #include <asm/arch/at91_gpbr.h>
29 
30 int rtc_get (struct rtc_time *tmp)
31 {
32 	at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
33 	at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
34 	ulong tim;
35 	ulong tim2;
36 	ulong off;
37 
38 	do {
39 		tim = readl(&rtt->vr);
40 		tim2 = readl(&rtt->vr);
41 	} while (tim!=tim2);
42 	off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
43 	/* off==0 means time is invalid, but we ignore that */
44 	rtc_to_tm(tim+off, tmp);
45 	return 0;
46 }
47 
48 int rtc_set (struct rtc_time *tmp)
49 {
50 	at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
51 	at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
52 	ulong tim;
53 
54 	tim = rtc_mktime(tmp);
55 
56 	/* clear alarm, set prescaler to 32768, clear counter */
57 	writel(32768+AT91_RTT_RTTRST, &rtt->mr);
58 	writel(~0, &rtt->ar);
59 	writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
60 	/* wait for counter clear to happen, takes less than a 1/32768th second */
61 	while (readl(&rtt->vr) != 0)
62 		;
63 	return 0;
64 }
65 
66 void rtc_reset (void)
67 {
68 	at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
69 	at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
70 
71 	/* clear alarm, set prescaler to 32768, clear counter */
72 	writel(32768+AT91_RTT_RTTRST, &rtt->mr);
73 	writel(~0, &rtt->ar);
74 	writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
75 	/* wait for counter clear to happen, takes less than a 1/32768th second */
76 	while (readl(&rtt->vr) != 0)
77 		;
78 }
79