1 /* 2 * Copyright (c) 2017 3 * Patrice Chotard <patrice.chotard@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <errno.h> 10 #include <wait_bit.h> 11 #include <dm.h> 12 #include <reset-uclass.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <dt-bindings/reset/stih407-resets.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 struct sti_reset { 20 const struct syscfg_reset_controller_data *data; 21 }; 22 23 /** 24 * Reset channel description for a system configuration register based 25 * reset controller. 26 * 27 * @compatible: Compatible string of the syscon containing this 28 * channel's control and ack (status) bits. 29 * @reset_offset: Reset register offset in sysconf bank. 30 * @reset_bit: Bit number in reset register. 31 * @ack_offset: Ack reset register offset in syscon bank. 32 * @ack_bit: Bit number in Ack reset register. 33 * @deassert_cnt: incremented when reset is deasserted, reset can only be 34 * asserted when equal to 0 35 */ 36 37 struct syscfg_reset_channel_data { 38 const char *compatible; 39 int reset_offset; 40 int reset_bit; 41 int ack_offset; 42 int ack_bit; 43 int deassert_cnt; 44 }; 45 46 /** 47 * Description of a system configuration register based reset controller. 48 * 49 * @wait_for_ack: The controller will wait for reset assert and de-assert to 50 * be "ack'd" in a channel's ack field. 51 * @active_low: Are the resets in this controller active low, i.e. clearing 52 * the reset bit puts the hardware into reset. 53 * @nr_channels: The number of reset channels in this controller. 54 * @channels: An array of reset channel descriptions. 55 */ 56 struct syscfg_reset_controller_data { 57 bool wait_for_ack; 58 bool active_low; 59 int nr_channels; 60 struct syscfg_reset_channel_data *channels; 61 }; 62 63 /* STiH407 Peripheral powerdown definitions. */ 64 static const char stih407_core[] = "st,stih407-core-syscfg"; 65 static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg"; 66 static const char stih407_lpm[] = "st,stih407-lpm-syscfg"; 67 68 #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \ 69 { .compatible = _c, \ 70 .reset_offset = _rr, \ 71 .reset_bit = _rb, \ 72 .ack_offset = _ar, \ 73 .ack_bit = _ab, } 74 75 #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \ 76 { .compatible = _c, \ 77 .reset_offset = _rr, \ 78 .reset_bit = _rb, } 79 80 #define STIH407_SRST_CORE(_reg, _bit) \ 81 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) 82 83 #define STIH407_SRST_SBC(_reg, _bit) \ 84 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) 85 86 #define STIH407_SRST_LPM(_reg, _bit) \ 87 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) 88 89 #define STIH407_PDN_0(_bit) \ 90 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit) 91 #define STIH407_PDN_1(_bit) \ 92 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit) 93 #define STIH407_PDN_ETH(_bit, _stat) \ 94 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat) 95 96 /* Powerdown requests control 0 */ 97 #define SYSCFG_5000 0x0 98 #define SYSSTAT_5500 0x7d0 99 /* Powerdown requests control 1 (High Speed Links) */ 100 #define SYSCFG_5001 0x4 101 #define SYSSTAT_5501 0x7d4 102 103 /* Ethernet powerdown/status/reset */ 104 #define SYSCFG_4032 0x80 105 #define SYSSTAT_4520 0x820 106 #define SYSCFG_4002 0x8 107 108 static struct syscfg_reset_channel_data stih407_powerdowns[] = { 109 [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1), 110 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0), 111 [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6), 112 [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5), 113 [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4), 114 [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3), 115 [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2), 116 [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1), 117 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0), 118 [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2), 119 }; 120 121 /* Reset Generator control 0/1 */ 122 #define SYSCFG_5128 0x200 123 #define SYSCFG_5131 0x20c 124 #define SYSCFG_5132 0x210 125 126 #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */ 127 128 static struct syscfg_reset_channel_data stih407_softresets[] = { 129 [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4), 130 [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3), 131 [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28), 132 [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29), 133 [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30), 134 [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6), 135 [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6), 136 [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15), 137 [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7), 138 [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16), 139 [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4), 140 [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13), 141 [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22), 142 [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5), 143 [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14), 144 [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3), 145 [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10), 146 [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11), 147 [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12), 148 [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14), 149 [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15), 150 [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21), 151 [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23), 152 [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24), 153 [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30), 154 [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0), 155 [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1), 156 [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2), 157 [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8), 158 [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26), 159 [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27), 160 [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28), 161 [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2), 162 }; 163 164 /* PicoPHY reset/control */ 165 #define SYSCFG_5061 0x0f4 166 167 static struct syscfg_reset_channel_data stih407_picophyresets[] = { 168 [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5), 169 [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6), 170 [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7), 171 }; 172 173 static const struct 174 syscfg_reset_controller_data stih407_powerdown_controller = { 175 .wait_for_ack = true, 176 .nr_channels = ARRAY_SIZE(stih407_powerdowns), 177 .channels = stih407_powerdowns, 178 }; 179 180 static const struct 181 syscfg_reset_controller_data stih407_softreset_controller = { 182 .wait_for_ack = false, 183 .active_low = true, 184 .nr_channels = ARRAY_SIZE(stih407_softresets), 185 .channels = stih407_softresets, 186 }; 187 188 static const struct 189 syscfg_reset_controller_data stih407_picophyreset_controller = { 190 .wait_for_ack = false, 191 .nr_channels = ARRAY_SIZE(stih407_picophyresets), 192 .channels = stih407_picophyresets, 193 }; 194 195 phys_addr_t sti_reset_get_regmap(const char *compatible) 196 { 197 struct udevice *syscon; 198 struct regmap *regmap; 199 int node, ret; 200 201 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 202 compatible); 203 if (node < 0) { 204 error("unable to find %s node\n", compatible); 205 return node; 206 } 207 208 ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon); 209 if (ret) { 210 error("%s: uclass_get_device_by_of_offset failed: %d\n", 211 __func__, ret); 212 return ret; 213 } 214 215 regmap = syscon_get_regmap(syscon); 216 if (!regmap) { 217 error("unable to get regmap for %s\n", syscon->name); 218 return -ENODEV; 219 } 220 221 return regmap->base; 222 } 223 224 static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert) 225 { 226 struct udevice *dev = reset_ctl->dev; 227 struct syscfg_reset_controller_data *reset_desc = 228 (struct syscfg_reset_controller_data *)(dev->driver_data); 229 struct syscfg_reset_channel_data *ch; 230 phys_addr_t base; 231 u32 ctrl_val = reset_desc->active_low ? !assert : !!assert; 232 void __iomem *reg; 233 234 /* check if reset id is inside available range */ 235 if (reset_ctl->id >= reset_desc->nr_channels) 236 return -EINVAL; 237 238 /* get reset sysconf register base address */ 239 base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible); 240 241 ch = &reset_desc->channels[reset_ctl->id]; 242 243 /* check the deassert counter to assert reset when it reaches 0 */ 244 if (!assert) { 245 ch->deassert_cnt++; 246 if (ch->deassert_cnt > 1) 247 return 0; 248 } else { 249 if (ch->deassert_cnt > 0) { 250 ch->deassert_cnt--; 251 if (ch->deassert_cnt > 0) 252 return 0; 253 } else 254 error("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n", 255 reset_ctl, reset_ctl->dev, reset_ctl->id); 256 } 257 258 reg = (void __iomem *)base + ch->reset_offset; 259 260 if (ctrl_val) 261 generic_set_bit(ch->reset_bit, reg); 262 else 263 generic_clear_bit(ch->reset_bit, reg); 264 265 if (!reset_desc->wait_for_ack) 266 return 0; 267 268 reg = (void __iomem *)base + ch->ack_offset; 269 if (wait_for_bit(__func__, reg, BIT(ch->ack_bit), ctrl_val, 270 1000, false)) { 271 error("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n", 272 reset_ctl, reset_ctl->dev, reset_ctl->id); 273 274 return -ETIMEDOUT; 275 } 276 277 return 0; 278 } 279 280 static int sti_reset_request(struct reset_ctl *reset_ctl) 281 { 282 return 0; 283 } 284 285 static int sti_reset_free(struct reset_ctl *reset_ctl) 286 { 287 return 0; 288 } 289 290 static int sti_reset_assert(struct reset_ctl *reset_ctl) 291 { 292 return sti_reset_program_hw(reset_ctl, true); 293 } 294 295 static int sti_reset_deassert(struct reset_ctl *reset_ctl) 296 { 297 return sti_reset_program_hw(reset_ctl, false); 298 } 299 300 struct reset_ops sti_reset_ops = { 301 .request = sti_reset_request, 302 .free = sti_reset_free, 303 .rst_assert = sti_reset_assert, 304 .rst_deassert = sti_reset_deassert, 305 }; 306 307 static int sti_reset_probe(struct udevice *dev) 308 { 309 struct sti_reset *priv = dev_get_priv(dev); 310 311 priv->data = (void *)dev_get_driver_data(dev); 312 313 return 0; 314 } 315 316 static const struct udevice_id sti_reset_ids[] = { 317 { 318 .compatible = "st,stih407-picophyreset", 319 .data = (ulong)&stih407_picophyreset_controller, 320 }, 321 { 322 .compatible = "st,stih407-powerdown", 323 .data = (ulong)&stih407_powerdown_controller, 324 }, 325 { 326 .compatible = "st,stih407-softreset", 327 .data = (ulong)&stih407_softreset_controller, 328 }, 329 { } 330 }; 331 332 U_BOOT_DRIVER(sti_reset) = { 333 .name = "sti_reset", 334 .id = UCLASS_RESET, 335 .of_match = sti_reset_ids, 336 .probe = sti_reset_probe, 337 .priv_auto_alloc_size = sizeof(struct sti_reset), 338 .ops = &sti_reset_ops, 339 }; 340